Re: [PATCH v16 5/7] spi: pxa2xx: disable DMA for Apple MacBook8,1

[Shih-Yuan Lee (FourDollars)]

Hi Andy,

Thank you for the detailed feedback and for explaining the SoC-level
interrupt architecture.

> Neither is preferred until we will fully understand what's going on there.
> Yes, DMI quirk is a last resort, but to come to that we need to try better
> options. See my other reply about the DMA case.

I completely agree that DMI quirks should be a last resort when better
options exist. I have removed the custom force_pio module parameter
from the series.

Having investigated the ACPI resource options and confirmed via MMIO
that the EFI firmware permanently holds the LPSS DMA hardware block in
reset (LPSS_PRIV_RESETS = 0x0), applying a targeted DMI quirk in
spi-pxa2xx-pci.c appears to be the unavoidable last resort required to
prevent system hangs on this platform.

> It's impossible. The interrupt line from DMA controller is an IOAPIC RTE that
> is programmed by BIOS, there is no "physical wire" in traditional meaning.

Thank you for the correction regarding PCH SoC interrupt routing. You
are completely right that within the PCH die, LPSS interrupts use
IOAPIC RTEs rather than discrete physical PCB traces.

> No, this analysis is wrong. There are up to 3 interrupts that may participate
> in the design: DMA controller; SPI controller; and SPI peripheral. The first
> two usually use IOAPIC RTEs for the interrupts (and hence represented as
> Interrupt() resources in _CRS methods on DSDT, plus CSRT for DMA), and the
> last one often is GpioInt() and has nothing to do with DMA at all.

Thank you for clarifying the three distinct interrupts involved in LPSS systems:

  1. DMA controller interrupt (dw:dmac)
  2. SPI controller interrupt (00:15.4)
  3. SPI peripheral interrupt (GpioInt())

On MacBook8,1, the applespi input device specifically uses the third
mechanism: a dedicated Out-Of-Band GpioInt() line (TPAD_SPI_INT_L)
connected to the PCH GPIO controller to drive SPI keyboard and
trackpad transfers in PIO mode.

> For old hardware (before Skylake) LPSS DMA interrupt line is defined in
> two places: DSDT (and/or PCI) and CSRT. Changing in one might not help
> as CSRT may have something different. Check drivers/dma/acpi-dma.c
> acpi_dma_parse_resource_group().

Thanks for the pointer regarding CSRT on pre-Skylake platforms.

Direct MMIO inspection of the LPSS DMA controller (PCI device 00:15.0)
on physical MacBook8,1 hardware reveals that Apple's EFI firmware
leaves the functional reset register (LPSS_PRIV_RESETS at BAR0 +
0x204) permanently set to 0x00000000 (held in reset).

Since the LPSS DMA controller is held in reset (0x0) by EFI firmware
and the SPI peripheral relies on the dedicated OOB GpioInt() line for
PIO transfers, forcing PIO mode via the DMI quirk in spi-pxa2xx-pci.c
accurately reflects how EFI configures the hardware, allowing the
driver to operate reliably out-of-the-box without system hangs.

I have compiled the complete MMIO register dumps, schematic
references, and physical hardware test logs in a technical report for
reference [0]:

Thanks,
Shih-Yuan

[0]: https://github.com/fourdollars/MacBook8-1/blob/main/spi-keyboard-touchpad-technical-evidence-report.md