[PATCH] iio: pressure: dps310: fix pressure result shift bit definition

[Rupesh Majhi]

DPS310_PRS_SHIFT_EN is defined as BIT(4), but P_SHIFT is bit 2 of
CFG_REG. Bit 4 is INT_PRS, which enables the pressure measurement ready
interrupt on the SDO pin.

The datasheet requires the pressure result bit-shift to be enabled when
the oversampling rate is higher than 8 times, so
dps310_set_pres_precision() sets it for oversampling ratios of 16 and
above. With the wrong definition it leaves P_SHIFT clear and toggles the
pressure ready interrupt instead, so the result register is never shifted
and the pressure values read at those oversampling ratios are wrong.

Define the bit at its documented position. Temperature is not affected,
T_SHIFT is bit 3 and DPS310_TMP_SHIFT_EN already matches it.

Fixes: d711a3c7dc82 ("iio: dps310: Add pressure sensing capability")
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Rupesh Majhi <zoone.rupert@xxxxxxxxx>
---
Found by inspection while working on FIFO support, and checked against the
DPS310 datasheet V1.1 (2019-07-11), section 8.6 "Interrupt and FIFO
configuration (CFG_REG)", where the bit table reads INT_HL, INT_FIFO,
INT_TMP, INT_PRS, T_SHIFT, P_SHIFT, FIFO_EN, SPI_MODE for bits 7 down to 0.

Not tested on hardware yet: the driver probes and reads correctly under
qemu-system-arm -M rainier-bmc, but QEMU's DPS310 model does not implement
the shift bits, so it cannot show the difference. I have a DPS310 breakout
on order and can confirm the raw pressure values at oversampling >= 16 once
it arrives, if you would rather wait for that.

 drivers/iio/pressure/dps310.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/pressure/dps310.c b/drivers/iio/pressure/dps310.c
index 45bdb8c7670f..473973dd0694 100644
--- a/drivers/iio/pressure/dps310.c
+++ b/drivers/iio/pressure/dps310.c
@@ -50,7 +50,7 @@
 #define DPS310_CFG_REG		0x09
 #define  DPS310_INT_HL		BIT(7)
 #define  DPS310_TMP_SHIFT_EN	BIT(3)
-#define  DPS310_PRS_SHIFT_EN	BIT(4)
+#define  DPS310_PRS_SHIFT_EN	BIT(2)
 #define  DPS310_FIFO_EN		BIT(5)
 #define  DPS310_SPI_EN		BIT(6)
 #define DPS310_RESET		0x0c
-- 
2.43.0