Re: [PATCH net-next v5] net: phy: Add driver for Motorcomm Quad 2.5GbE phy

[Kyle Switch]

On 7/26/26 22:51, Andrew Lunn wrote:
> On Sun, Jul 26, 2026 at 11:24:16AM +0800, Kyle Switch wrote:
>>
>>
>> On 7/24/26 21:18, Andrew Lunn wrote:
>>>> Ans: It is different from the m88e1111 PHY, which may support UTP, fiber, 
>>>>      or combo mode. However, the PHY8824 is only used with UTPs, and 
>>>>      its structure is as follows, which includes UTP0, UTP1,UTP2,UTP3 and USXGMII.
>>>>
>>>>      RJ45 <----> UTP0 <------>
>>>>      RJ45 <----> UTP1 <------>   USXGMII  <----->  USXGMII(the side of MAC)
>>>>      RJ45 <----> UTP2 <------>
>>>>      RJ45 <----> UTP3 <------>
>>>>
>>>>      It is similar to phy8821 driver in motorcomm.c, with the difference 
>>>>      being that one has one UTP port and phy8824 has four UTP ports.
>>>>      YT8824_RSSR_FIBER_SPACE is used to access USXGMII reg space, Perhaps it 
>>>>      would be more accurate to call it YT8824_RSSR_USXGMII_SPACE or 
>>>>      YT8824_RSSR_SERDES_SPACE.
>>>
>>> O.K, that completely changes my understanding of this device. Yes,
>>> YT8824_RSSR_FIBER_SPACE should change name. And i would include this
>>> diagram in the driver, and indicate how YT8824_RSSR_*_SPACE map to
>>> this.
>>>
>>> For the locking, look thought all the code which is touching the
>>> USXGMII side and see if it can be moved into probe().
>>>
>>
>> Ans: It may not be possible to completely move the code which touch the USXGMII side
>>      into the probe() function. The initialization configuration aimed at optimizing 
>>      the performance of the USXGMII side may be moved into the probe(). However, for the 
>>      soft reset of UTP, it is necessary to configure MII_BMCR registers in USXGMII side.
> 
> I'm beginning to think you need to add an extra lock.
> 
> The idea with the mdio lock for accessing pages was that is existed,
> and it would protect against accesses which don't come through phylib,
> like hwmon. Because it is a low level lock, it really only works
> within one PHY, when there are operations going on above it. The
> assumption is that PHYs operate independently.
> 
> You are attempting to use it differently. Because of the poor hardware
> design, you need to protect one PHY from another PHY. Your PHYs don't
> operate independently. So i think you need to add a high level lock,
> shared across the package. All the entry points via struct phy_driver
> need to lock the package as a whole. The PHY can then do what it needs
> to do without having to worry about another PHY being operated on in
> parallel. You can make use of the phylib helpers, since the MDIO level
> lock is not taken. phylibs concept of pages registers will work. Once
> everything is done, release the package lock.
> 
> So, please look at adding phy_package_lock() and
> phy_package_unlock(). Maybe it is possible to make use of struct
> mii_bus shared_lock? Please look at how that is currently used and
> check to see if there might be deadlocks.
> 

Ans: From my perspective, although a phy8824 has four UTPs, it uses the same mdio bus. 
     Wouldn't it be possible to achieve the desired effect without using an extra lock.

     There are only two scenarios for phy8824 to swap to USXGMII reg space.
     1. init configuration 
     2. soft reset and isolate done in USXGMII side during UTP soft reset.

     for scenario 1:
     It will lock the MDIO bus throughout the entire process, and upon completion, 
     it will swap to the UTP register space and unlock the MDIO bus.

     For scenario 2:
     If PHY1 works on its own UTP reg space, at this point, PHY2 swap the reg space to USXGMII side.
     In this case, PHY2 will hold this lock until the operation of PHY2 is completed, 
     and swap back to UTP reg space, unlock the bus. It will not affect the operation of PHY1
     works on its own UTP reg space.
>       Andrew