[PATCH 3/4] arm64: dts: qcom: sm8550-hdk: Enable I2S for HDMI

From: Neil Armstrong

Date: Tue Jul 28 2026 - 05:06:33 EST


Add the necessary nodes to configure the right I2S interface
to output audio via the DSI HDMI bridge.

Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 36 +++++++++++++++-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 73 +++++++++++++++++++++++++++++++++
2 files changed, 108 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index ee13e6136a82..87792fbf3323 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -278,6 +278,22 @@ platform {
sound-dai = <&q6apm>;
};
};
+
+ prim-mi2s-dai-link {
+ link-name = "HDMI Playback";
+
+ cpu {
+ sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>;
+ };
+
+ codec {
+ sound-dai = <&lt9611_codec 0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
};

wcn7850-pmu {
@@ -888,9 +904,14 @@ lt9611_codec: hdmi-bridge@2b {
vdd-supply = <&lt9611_1v2>;
vcc-supply = <&lt9611_3v3>;

- pinctrl-0 = <&lt9611_irq_pin>, <&lt9611_rst_pin>;
+ pinctrl-0 = <&lt9611_irq_pin>,
+ <&lt9611_rst_pin>,
+ <&i2s0_default_state>,
+ <&audio_mclk0_default_state>;
pinctrl-names = "default";

+ #sound-dai-cells = <1>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1144,6 +1165,19 @@ pmk8550_sleep_clk: sleep-clk-state {
};
};

+&q6apmbedai {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dai@16 {
+ reg = <PRIMARY_MI2S_RX>;
+ clocks = <&q6prmcc LPASS_CLK_ID_MCLK_1 LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_CLK_ID_PRI_MI2S_IBIT LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "mclk",
+ "bclk";
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 396201905ef2..5a2f88614cbc 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -5526,6 +5526,79 @@ data-pins {
drive-strength = <10>;
};
};
+
+ audio_mclk0_default_state: audio-mclk0-default-state {
+ pins = "gpio125";
+ function = "audio_ext_mclk0";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ i2s0_default_state: i2s0-default-state {
+ sck-pins {
+ pins = "gpio126";
+ function = "i2s0_sck";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ data0-pins {
+ pins = "gpio127";
+ function = "i2s0_data0";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ data1-pins {
+ pins = "gpio128";
+ function = "i2s0_data1";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ ws-pins {
+ pins = "gpio129";
+ function = "i2s0_ws";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ audio_mclk1_default_state: audio-mclk1-default-state {
+ pins = "gpio124";
+ function = "audio_ext_mclk1";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ i2s1_default_state: i2s1-default-state {
+ sck-pins {
+ pins = "gpio121";
+ function = "i2s1_sck";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ data0-pins {
+ pins = "gpio122";
+ function = "i2s1_data0";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ ws-pins {
+ pins = "gpio123";
+ function = "i2s1_ws";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+ };
};

sram@14680000 {

--
2.34.1