[PATCH RFC 6/7] riscv: dts: spacemit: k3: Fix SSWI node misidentified as CLINT

From: Junhui Liu

Date: Tue Jul 28 2026 - 12:43:49 EST


The previous Device Tree defined a legacy CLINT node at 0xe081c000.
However, this register space actually belongs to the ACLINT SSWI
controller. Correct the node definition and compatible string so that
SSWI functions properly.

The ACLINT SSWI device can be accessed at either 0xf181c000 (secure) or
0xe081c000 (non-secure). However, there is an efuse bit that controls
access to the secure alias: when enabled, it restricts access solely to
Machine mode. Therefore, the non-secure base address is chosen for the
kernel to drive SSWI reliably.

Fixes: 56f37e391a62 ("riscv: dts: spacemit: add initial support for K3 SoC")
Signed-off-by: Junhui Liu <junhui.liu@xxxxxxxxxxxxx>
---
arch/riscv/boot/dts/spacemit/k3.dtsi | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index c3f2dce0969c..5fb719f79467 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -1261,17 +1261,15 @@ saplic: interrupt-controller@e0804000 {
riscv,num-sources = <512>;
};

- clint: timer@e081c000 {
- compatible = "spacemit,k3-clint", "sifive,clint0";
+ aclint_sswi: interrupt-controller@e081c000 {
+ compatible = "spacemit,k3-aclint-sswi", "riscv,aclint-sswi";
reg = <0x0 0xe081c000 0x0 0x4000>;
- interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
- <&cpu1_intc 3>, <&cpu1_intc 7>,
- <&cpu2_intc 3>, <&cpu2_intc 7>,
- <&cpu3_intc 3>, <&cpu3_intc 7>,
- <&cpu4_intc 3>, <&cpu4_intc 7>,
- <&cpu5_intc 3>, <&cpu5_intc 7>,
- <&cpu6_intc 3>, <&cpu6_intc 7>,
- <&cpu7_intc 3>, <&cpu7_intc 7>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 1>, <&cpu1_intc 1>,
+ <&cpu2_intc 1>, <&cpu3_intc 1>,
+ <&cpu4_intc 1>, <&cpu5_intc 1>,
+ <&cpu6_intc 1>, <&cpu7_intc 1>;
};

/* sec_i2c3: 0xf0614000, not available from Linux */

--
2.55.0