Re: [PATCH v8 01/12] dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller

[Stefan Dösinger]

Hi Krzysztof,

Thanks for the prompt review!

> Am 28.07.2026 um 09:27 schrieb Krzysztof Kozlowski <krzk@xxxxxxxxxx>:
> 
>> 
>> +  resets:
>> +    items:
>> +      - description: USB phy reset
>> +      - description: HSIC phy reset
>> +
>> +  reset-names:
>> +    items:
>> +      - const: usb
>> +      - const: hsic
> 
> You do not need these two. It's one device and DT does not represent
> internal device wirings because they are redundant (deducible from the
> compatible).

Just to make sure I understand the implications: Remove the PHY resets from the reset header (and driver) and have the PHY driver control them directly via regmap instead of going through its reset sibling? That way no self-consumption is necessary. At least that's the idea Sashiko put into my head with "Could the driver interact with its own registers directly?".

The PHY driver would take exclusive ownership of the resets anyhow, so I don't see anything in the way of just making it own the respective bits in the 0x80 register through the shared regmap.

>> +required:
>> +  - compatible
>> +  - reg
>> +  - clocks
>> +  - clock-names
>> +  - interrupts
>> +  - interrupt-names
>> +  - resets
>> +  - reset-names
>> +  - syscon-reboot
>> +  - "#clock-cells"
>> +  - "#phy-cells"
>> +  - "#reset-cells"
>> +
>> +unevaluatedProperties: false
> 
> This was different last time and previous code was correct.

Ok, I'll keep #phy-cells and ints optional and also make it possible to provide only USB or HSIC ints.

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