Re: [RFC PATCH 07/13] arm64: percpu: Implement preemptible read/write ops

[David Laight]

On Tue, 28 Jul 2026 13:38:53 +0100
Mark Rutland <mark.rutland@xxxxxxx> wrote:

> Use the PCPU GPR infrastructure to implement preemptible this_cpu_read()
> and this_cpu_write().
> 
> Note that this change means that this_cpu_read() will always use a plain
> LDR, even in LTO configurations where READ_ONCE() will use LDA[P]R. I
> am not sure whether that's ok, or whether we should similarly use
> LDA[P]R here.
> 
...
> Generated code after this patch:
> 
> | <outline_this_cpu_write_u64>:
> |        mrs     x2, sp_el0
> |        mov     w3, #0x7c60
> |        strh    w3, [x2, #20]
> |        mrs     x3, tpidr_el1
> |        str     x1, [x0, x3]
> |        strh    wzr, [x2, #20]
> |        ret

How is that likely to get scheduled on a typical arm64 cpu?
In particular does the reuse of [wx]3 create a register dependency
between the two instruction flows and stop then running in parallel.
A typical x86 cpu (that anyone cares about) does register renaming
so it wouldn't matter, but I don't know about arm.
So it might be worth using different register for w3 and x3 (although
that might cause a spill - which will be worse).

	David