[PATCH v2 1/2] dt-bindings: gpio: Add Axiado SGPIO controller
From: Petar Stepanovic
Date: Wed Jul 29 2026 - 03:12:54 EST
Add a Devicetree binding for the SGPIO controller found on the
Axiado AX3000 and AX3005 SoCs.
Each SGPIO position provides one fixed-direction input GPIO and one
fixed-direction output GPIO. Input GPIOs support edge-triggered
interrupts.
The controller serializes output values and samples input values over
dedicated data, clock, and latch signals.
Signed-off-by: Petar Stepanovic <pstepanovic@xxxxxxxxxx>
---
.../devicetree/bindings/gpio/axiado,sgpio.yaml | 118 +++++++++++++++++++++
MAINTAINERS | 8 ++
2 files changed, 126 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpio/axiado,sgpio.yaml b/Documentation/devicetree/bindings/gpio/axiado,sgpio.yaml
new file mode 100644
index 000000000000..448f01c367dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/axiado,sgpio.yaml
@@ -0,0 +1,118 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/axiado,sgpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Axiado SGPIO Controller
+
+maintainers:
+ - Petar Stepanovic <pstepanovic@xxxxxxxxxx>
+ - SriNavmani A <srinavmani@xxxxxxxxxx>
+ - Prasad Bolisetty <pbolisetty@xxxxxxxxxx>
+
+description: |
+ The Axiado SGPIO controller provides a serial GPIO expansion interface
+ that multiplexes multiple GPIO signals over a small set of physical lines.
+
+ The controller operates as a shift-based interface, where output values
+ are serialized on a data output line and input values are sampled from a
+ data input line in synchronization with a shift clock. A latch signal is
+ used to update output states after each transfer cycle.
+
+ The interface uses data output (DOUT), data input (DIN), shift clock
+ (SCLK), and latch signal (LATCH).
+
+ Each SGPIO position provides one fixed-direction input GPIO and one
+ fixed-direction output GPIO. Input GPIOs support edge-triggered
+ interrupts.
+
+ GPIOs are organized in banks of 32 signals, with registers controlling
+ output values, input sampling, and interrupt status. The number of GPIO
+ lines depends on the hardware variant.
+
+ The controller detects changes on input GPIOs. Interrupt events are
+ aggregated and signaled through a single interrupt line to the parent
+ interrupt controller.
+
+ Register access is performed over the APB bus. The SGPIO shift clock is
+ derived from the APB clock using a programmable divider.
+
+properties:
+ compatible:
+ enum:
+ - axiado,ax3000-sgpio
+ - axiado,ax3005-sgpio
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description:
+ APB clock used for register access and SGPIO shift clock generation
+ maxItems: 1
+
+ bus-frequency:
+ description: SGPIO shift clock frequency in Hz
+ minimum: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+ ngpios:
+ description:
+ Number of SGPIO positions. Each position provides one input GPIO and
+ one output GPIO.
+ enum: [128, 512]
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ const: axiado,ax3000-sgpio
+ then:
+ properties:
+ ngpios:
+ const: 128
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - bus-frequency
+ - gpio-controller
+ - '#gpio-cells'
+ - interrupt-controller
+ - '#interrupt-cells'
+ - interrupts
+ - ngpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ sgpio@a000 {
+ compatible = "axiado,ax3005-sgpio";
+ reg = <0xa000 0x800>;
+ clocks = <&apb_clk>;
+ bus-frequency = <1000000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ ngpios = <128>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index a674e36529f7..fc613271f435 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4407,6 +4407,14 @@ S: Orphan
F: Documentation/devicetree/bindings/sound/axentia,*
F: sound/soc/atmel/tse850-pcm5142.c
+AXIADO SGPIO DRIVER
+M: Petar Stepanovic <pstepanovic@xxxxxxxxxx>
+M: SriNavmani A <srinavmani@xxxxxxxxxx>
+M: Prasad Bolisetty <pbolisetty@xxxxxxxxxx>
+L: linux-gpio@xxxxxxxxxxxxxxx
+S: Supported
+F: Documentation/devicetree/bindings/gpio/axiado,sgpio.yaml
+
AXIS ARTPEC ARM64 SoC SUPPORT
M: Jesper Nilsson <jesper.nilsson@xxxxxxxx>
M: Lars Persson <lars.persson@xxxxxxxx>
--
2.34.1