Re: [PATCH net-next v2] net: stmmac: dwxgmac2: configure INTM for per-channel interrupt routing

[Qingfang Deng]

On 2026/7/29 10:36, Zxyan Zhu wrote:
> The XGMAC DMA_MODE register has an INTM field (bits 13:12) that
> controls interrupt routing behavior for DMA transfer completion
> events:
>
>    00 (default): sbd_perch_* are pulse signals, sbd_intr_o is also
>                  asserted for each completion event.
>    01:          sbd_perch_* are level signals, sbd_intr_o is NOT
>                  asserted for packet transfer completion events.
>
> When multi-MSI is enabled, per-channel TX/RX interrupts are expected
> to arrive on their dedicated lines.  In the default INTM=00 mode,
> sbd_intr_o also fires for DMA completion events, but the multi-MSI
> handler stmmac_mac_interrupt() only processes MAC-layer events (LPI,
> PMT, timestamps) and returns IRQ_NONE for every DMA completion
> interrupt, resulting in a continuous stream of unhandled interrupts
> on the common IRQ.
>
> Hardware verification with XGMAC and multi-MSI enabled:
>
>    INTM=00: 5.4 million common IRQ interrupts in 3 seconds, ~1.8
>             million IRQ_NONE returns per second.
>    INTM=01: 0 common IRQ interrupts, per-channel IRQs work normally,
>             10G line rate works correctly.
>
> Set INTM to mode 1 when multi-MSI is enabled.  This matches the
> existing GMAC4 implementation.
>
> XGMAC multi-MSI has never worked correctly since it was introduced.
>
> Signed-off-by: Zxyan Zhu <zxyan0222@xxxxxxxxx>

As someone who has written an out-of-tree driver for the DW XGMAC:

Reviewed-by: Qingfang Deng <qingfang.deng@xxxxxxxxx>