[PATCH 2/3] arm64: dts: imx91: Assign media_{axi,apb}_root clock parents/rates
From: Liu Ying
Date: Wed Jul 29 2026 - 05:46:58 EST
According to i.MX91 SoC reference manual, maximal clock frequencies
in nominal drive mode for media_axi_root and media_apb_root clocks
are 333.33MHz and 125MHz respectively. Assign the clock parents to
be IMX93_CLK_SYS_PLL_PFD0 @ 1GHz and IMX93_CLK_SYS_PLL_PFD0_DIV2 @
500MHz respectively and assign the maximal clock rates by overriding
the original settings in imx91_93_common.dtsi. This would effectively
achieve media_axi_root clock running at 333.333334MHz and media_apb_root
clock running at 125MHz, which aligns to NXP downstream kernel settings.
Signed-off-by: Liu Ying <victor.liu@xxxxxxx>
---
arch/arm64/boot/dts/freescale/imx91.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi
index df2532835bb8..a7355f533d70 100644
--- a/arch/arm64/boot/dts/freescale/imx91.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx91.dtsi
@@ -120,6 +120,13 @@ &media_blk_ctrl {
<&clk IMX93_CLK_MIPI_CSI_GATE>;
clock-names = "apb", "axi", "nic", "disp", "cam",
"lcdif", "isi", "csi";
+ assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>,
+ <&clk IMX93_CLK_MEDIA_APB>,
+ <&clk IMX93_CLK_MEDIA_DISP_PIX>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD0>,
+ <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
+ <&clk IMX93_CLK_VIDEO_PLL>;
+ assigned-clock-rates = <333330000>, <125000000>;
};
&ocotp {
--
2.43.0