Re: [PATCH v14 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema

[Vladimir Zapolskiy]

On 7/27/26 23:06, Bryan O'Donoghue wrote:
> On 27/07/2026 21:03, Vladimir Zapolskiy wrote:
> > > +                description:
> > > +                  Logical lane indices 0-3, not physical pad positions.
> >
> > In hardware description it's physical data lane indexes, the same is
> > said in
> > video-interfaces.yaml documentation, the numeration starting from zero is
> > selected to follow even bits in CSI_COMMON_CTRL5 register (D-PHY mode):
> >
> > * https://lore.kernel.org/
> > all/59331aa7-8430-4754-861c-4ba6a4810ccd@xxxxxxxxxxxxxxxx/
>
> I'm not sure what you're asking for here - this exact text ?

Returning to the description of 'data-lanes' property:

> Logical lane indices 0-3, not physical pad positions.

Logical lane index is the same as a position of a physical lane index in
the 'data-lanes' array, this array data cannot be "logical lane indices".

A valid description is found in video-interfaces.yaml: "An array of
physical  data lane indexes". So, it should be an array, and specifically
an array of physical data lane indices, this contradicts to the given
description for CSIPHY.

Here the open question is how physical lanes of CSIPHY are numerated, this
requires a verbose comment. For instance Qualcomm CSIPHY configured in D-PHY
combo mode (two sensors attached) has 2 or 3 data lanes and 2 clock lanes,
for such and other cases a 'data-lanes' property description should be clear
and unambiguous to allow a valid configuration to be provided.

--
Best wishes,
Vladimir