[PATCH 03/10] dt-bindings: clock: add Ambarella CV75 RCT clock controller

[Long Zhao]

Add the CV75 RCT clock controller binding and clock ID header.

Signed-off-by: Long Zhao <longzhao@xxxxxxxxxxxxx>
---
 .../bindings/clock/ambarella,cv75-rct.yaml    | 94 +++++++++++++++++++
 .../dt-bindings/clock/ambarella,cv75-clock.h  | 17 ++++
 2 files changed, 111 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml
 create mode 100644 include/dt-bindings/clock/ambarella,cv75-clock.h

diff --git a/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml b/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml
new file mode 100644
index 000000000000..5ff5b6a4a0b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ambarella,cv75-rct.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ambarella CV75 RCT Clock Controller
+
+maintainers:
+  - Long Zhao <longzhao@xxxxxxxxxxxxx>
+
+description: |
+  The RCT (Reset and Clock Tree) block on the Ambarella CV75 SoC provides
+  PLLs, clock muxes and dividers for on-chip peripherals.
+
+  The same register region is also exposed as a syscon for other drivers
+  (e.g. pin drive-strength), hence the "syscon" compatible.
+
+  Clock indices are defined in
+  include/dt-bindings/clock/ambarella,cv75-clock.h:
+
+  - CV75_GCLK_UART0: UART0 mux/div clock
+  - CV75_GCLK_CORE: Core PLL (gclk_core)
+  - CV75_GCLK_AHB: AHB bus clock (core / 2)
+  - CV75_GCLK_APB: APB bus clock (core / 4)
+
+allOf:
+  - $ref: /schemas/mfd/syscon-common.yaml#
+
+properties:
+  $nodename:
+    pattern: "^clock-controller(@.*)?$"
+
+  compatible:
+    items:
+      - const: ambarella,cv75-rct
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    description: Reference crystal oscillator (typically 24 MHz)
+    maxItems: 1
+
+  clock-names:
+    const: osc
+
+  "#clock-cells":
+    const: 1
+
+  assigned-clocks: true
+
+  assigned-clock-parents: true
+
+  assigned-clock-rates: true
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#clock-cells"
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/ambarella,cv75-clock.h>
+
+    / {
+        compatible = "ambarella,cv75-evk", "ambarella,cv75";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        osc: oscillator {
+            compatible = "fixed-clock";
+            #clock-cells = <0>;
+            clock-output-names = "osc";
+            clock-frequency = <24000000>;
+        };
+
+        rct: clock-controller@ed080000 {
+            compatible = "ambarella,cv75-rct", "syscon";
+            reg = <0xff 0xed080000 0x0 0x1000>;
+            clocks = <&osc>;
+            clock-names = "osc";
+            #clock-cells = <1>;
+
+            assigned-clocks = <&rct CV75_GCLK_UART0>;
+            assigned-clock-parents = <&osc>;
+            assigned-clock-rates = <24000000>;
+        };
+    };
diff --git a/include/dt-bindings/clock/ambarella,cv75-clock.h b/include/dt-bindings/clock/ambarella,cv75-clock.h
new file mode 100644
index 000000000000..3d3314446e75
--- /dev/null
+++ b/include/dt-bindings/clock/ambarella,cv75-clock.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) 2026 Ambarella, Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMBARELLA_CV75_CLOCK_H
+#define _DT_BINDINGS_CLOCK_AMBARELLA_CV75_CLOCK_H
+
+/* Boot / bus clocks */
+#define CV75_GCLK_UART0                0
+#define CV75_GCLK_CORE         1
+#define CV75_GCLK_AHB          2
+#define CV75_GCLK_APB          3
+
+#define CV75_CLK_NUM           4
+
+#endif
--
2.34.1

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