[PATCH v23 05/14] mmc: renesas_sdhi: Make clock divider mask configurable
From: Biju
Date: Thu Jul 30 2026 - 07:57:46 EST
From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Add a clk_div_mask field to renesas_sdhi_of_data and tmio_mmc_data
so each SoC can specify its own divider mask instead of the
hardcoded CLK_CTL_DIV_MASK used in renesas_sdhi_set_clock().
Default to GENMASK(7, 0) at probe time when unset, and populate all
existing internal/sys DMAC of_data tables with this value to keep
current SoCs unaffected. This lets RZ/G3L, which has a wider
divider field, reuse the same clock-setting code.
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
* Assigned of_data->clk_div_mask in renesas_sdhi_probe().
v21->v22:
* Updated commit description.
* Added clk_div_mask to of_default_cfg and of_rcar_gen2_compatible.
v21:
* New patch.
---
drivers/mmc/host/renesas_sdhi.h | 1 +
drivers/mmc/host/renesas_sdhi_core.c | 6 +++++-
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 3 +++
drivers/mmc/host/renesas_sdhi_sys_dmac.c | 4 ++++
include/linux/platform_data/tmio.h | 1 +
5 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h
index af56b4bfb1d4..9c72eb78e31e 100644
--- a/drivers/mmc/host/renesas_sdhi.h
+++ b/drivers/mmc/host/renesas_sdhi.h
@@ -41,6 +41,7 @@ struct renesas_sdhi_of_data {
unsigned long sdhi_flags;
u64 clk_mask;
int max_divider;
+ u16 clk_div_mask;
};
#define SDHI_CALIB_TABLE_MAX 32
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index d893a263e770..5dcbb431e1e1 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -224,7 +224,7 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
clk &= ~0xff;
}
- clock = clk & CLK_CTL_DIV_MASK;
+ clock = clk & host->pdata->clk_div_mask;
if (clock != CLK_CTL_DIV_MASK)
host->mmc->actual_clock /= (1 << (ffs(clock) + 1));
@@ -1138,6 +1138,7 @@ int renesas_sdhi_probe(struct platform_device *pdev,
mmc_data->max_segs = of_data->max_segs;
mmc_data->clk_mask = of_data->clk_mask;
mmc_data->max_divider = of_data->max_divider;
+ mmc_data->clk_div_mask = of_data->clk_div_mask;
dma_priv->dma_buswidth = of_data->dma_buswidth;
host->bus_shift = of_data->bus_shift;
/* Fallback for old DTs */
@@ -1186,6 +1187,9 @@ int renesas_sdhi_probe(struct platform_device *pdev,
if (!mmc_data->max_divider)
mmc_data->max_divider = SDHI_MAX_DIVIDER_DEFAULT;
+ if (!mmc_data->clk_div_mask)
+ mmc_data->clk_div_mask = GENMASK(7, 0);
+
dma_priv->filter = shdma_chan_filter;
dma_priv->enable = renesas_sdhi_enable_dma;
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index 2bf354331b2d..9bf7aa9bd867 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -103,6 +103,7 @@ static const struct renesas_sdhi_of_data of_data_rza2 = {
.max_segs = 1,
.clk_mask = SDHI_CLK_MASK_DEFAULT,
.max_divider = SDHI_MAX_DIVIDER_DEFAULT,
+ .clk_div_mask = GENMASK(7, 0),
};
static const struct renesas_sdhi_of_data of_data_rcar_gen3 = {
@@ -122,6 +123,7 @@ static const struct renesas_sdhi_of_data of_data_rcar_gen3 = {
.sdhi_flags = SDHI_FLAG_NEED_CLKH_FALLBACK,
.clk_mask = SDHI_CLK_MASK_DEFAULT,
.max_divider = SDHI_MAX_DIVIDER_DEFAULT,
+ .clk_div_mask = GENMASK(7, 0),
};
static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback = {
@@ -140,6 +142,7 @@ static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback = {
.max_segs = 1,
.clk_mask = SDHI_CLK_MASK_DEFAULT,
.max_divider = SDHI_MAX_DIVIDER_DEFAULT,
+ .clk_div_mask = GENMASK(7, 0),
};
static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
index bb66ff7de065..90e3bc6b954f 100644
--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
@@ -30,6 +30,7 @@ static const struct renesas_sdhi_of_data of_default_cfg = {
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
.clk_mask = SDHI_CLK_MASK_DEFAULT,
.max_divider = SDHI_MAX_DIVIDER_DEFAULT,
+ .clk_div_mask = GENMASK(7, 0),
};
static const struct renesas_sdhi_of_data of_rz_compatible = {
@@ -40,6 +41,7 @@ static const struct renesas_sdhi_of_data of_rz_compatible = {
MMC_CAP_WAIT_WHILE_BUSY,
.clk_mask = SDHI_CLK_MASK_DEFAULT,
.max_divider = SDHI_MAX_DIVIDER_DEFAULT,
+ .clk_div_mask = GENMASK(7, 0),
};
static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = {
@@ -49,6 +51,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = {
.capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
.clk_mask = SDHI_CLK_MASK_DEFAULT,
.max_divider = SDHI_MAX_DIVIDER_DEFAULT,
+ .clk_div_mask = GENMASK(7, 0),
};
/* Definitions for sampling clocks */
@@ -78,6 +81,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
.max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
.clk_mask = SDHI_CLK_MASK_DEFAULT,
.max_divider = SDHI_MAX_DIVIDER_DEFAULT,
+ .clk_div_mask = GENMASK(7, 0),
};
static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
diff --git a/include/linux/platform_data/tmio.h b/include/linux/platform_data/tmio.h
index e104718cf21f..e4232934c7fe 100644
--- a/include/linux/platform_data/tmio.h
+++ b/include/linux/platform_data/tmio.h
@@ -63,5 +63,6 @@ struct tmio_mmc_data {
unsigned short max_segs;
u64 clk_mask;
int max_divider;
+ u16 clk_div_mask;
};
#endif
--
2.43.0