Re: [PATCH] pinctrl: sunxi: A523: fix voltage withstand encoding

[Juan Manuel]

Hi Andre,

> There is more to enabling Ethernet on the box, though, right? The
> EMAC25M pin needs to be configured correctly - not even sure that
> works cleanly with mainline? And what are the delay values that work
> for you?

Right, the withstand fix alone isn't enough. Three things were needed to
get GMAC1 up on the OPi 4A:

1) The PJ pinmux. Mainline's rgmii1 group was missing PJ10, which left
   one RX signal unmapped, so I got rx_packets=0. The BSP muxes the full
   PJ0..PJ15 (16 pins) as function "gmac1" (mux 5); with all 16 mapped,
   RX comes alive. I don't mux any separate/dedicated 25 MHz clock-out
   pin beyond that gmac1 group, and the link is rock solid, so on this
   board the PHY's 25 MHz reference isn't provided by an extra SoC pin.

2) RGMII clock delays. The board has a Motorcomm YT8531 PHY:
     - phy-mode          = "rgmii-rxid"
     - PHY node          : rx-internal-delay-ps = 1900  (YT8531
RXC_DLY_EN, ~1.9ns)
     - MAC syscon        : tx-internal-delay-ps = 100
                           rx-internal-delay-ps = 0
   That combo gives a stable 1 Gbps / full-duplex link, 0% packet loss.

3) Your withstand encoding fix. Before it, the PJ bank was driven at 1.8V
   while the receiver sat in 3.3V mode, so RX was effectively deaf. With
   your patch RX reads correctly.

All of the above is validated on my board (2026-07-08): link up at
1 Gbps/full, ping 0% loss over a sustained transfer.

Thanks again for the withstand fix - glad the POW_MOD_SEL patch helped
connect the dots.

Cheers,
Juan