Re: [PATCH v22 net-next 07/12] net/nebula-matrix: add chip-wide hardware init/deinit implementation
From: Jakub Kicinski
Date: Thu Jul 30 2026 - 21:34:31 EST
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---
--- Patch [7]: [PATCH v22 net-next 07/12] net/nebula-matrix: add chip-wide hardware init/deinit implementation ---
commit c620485c32e37b926b2895bd18463f304a29e084
Author: illusion wang <illusion.wang@xxxxxxxxxxxxxxxxx>
net/nebula-matrix: add chip-wide hardware init/deinit implementation
This commit adds Leonis chip-wide hardware initialization and
deinitialization logic to setup the full datapath pipeline.
> diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
> index 1c136b9e30b2a..22690cb9cc32b 100644
> --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
> +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c
[ ... ]
> +static int nbl_shaping_eth_init(struct nbl_hw_mgt *hw_mgt, u8 eth_id, u8 speed)
> +{
> + union nbl_shaping_dvn_dport_u dvn_dport = { 0 };
> + union nbl_shaping_dport_u dport = { 0 };
[ ... ]
> + /* 2. write config words (valid=0, safe) */
> + dport.info.low = FIELD_PREP(DPORT_CIR_MASK, rate) |
> + FIELD_PREP(DPORT_PIR_MASK, rate) |
> + FIELD_PREP(DPORT_DEPTH_MASK, depth) |
> + FIELD_PREP(DPORT_CBS_MASK_LOW, depth & 0x3F);
> + dport.info.high = FIELD_PREP(DPORT_CBS_MASK_HIGH, depth >> 6) |
> + FIELD_PREP(DPORT_PBS_MASK, depth);
[ ... ]
> + nbl_hw_wr_regs(hw_mgt, NBL_SHAPING_DPORT_REG(eth_id), dport.data,
> + sizeof(dport));
[ ... ]
> diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
> index 1d6d614be7d69..8e59b9d2ab3b0 100644
> --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
> +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h
[ ... ]
> +union nbl_shaping_dport_u {
> + struct nbl_shaping_dport {
> + u64 low;
> + u64 high;
> + } info;
> + u32 data[NBL_SHAPING_DPORT_DWLEN];
> +};
[Severity: High]
Will this union alias cause corrupted hardware writes on big-endian
architectures?
When fields are populated using native u64 in nbl_shaping_eth_init(), for
example:
dport.info.low = FIELD_PREP(DPORT_CIR_MASK, rate) | ...
And then written via the u32 array alias:
nbl_hw_wr_regs(hw_mgt, NBL_SHAPING_DPORT_REG(eth_id), dport.data,
sizeof(dport));
On big-endian systems, the upper 32 bits of the 64-bit integer will map to
data[0] instead of the lower 32 bits. Does this result in malformed hardware
configuration for traffic shaping?