Re: [PATCH v5] arm64: dts: qcom: x1e80100: Add deepest idle state

[Bjorn Andersson]

On Wed, 15 Jul 2026 18:31:30 +0530, Maulik Shah wrote:
> CPU subsystem deepest idle state can lead SoC to low power mode like CxPC
> (chip rail power collapse). SoC deepest low power mode requires the PDC
> interrupt controller to wake up the SoC as the GIC interrupt controller
> is on Cx (chip rail) and will not be functional to wake up the CPU.
> 
> PDC monitors both direct SPI interrupts and GPIOs used as interrupts
> in SoC low power mode. Further all wake up capable interrupts gets routed
> via PDC to GIC when SoC is out of low power mode.
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: qcom: x1e80100: Add deepest idle state
      commit: 95f827ceb21e2885f40eec5d93a340abbcc22d13

Best regards,
-- 
Bjorn Andersson <andersson@xxxxxxxxxx>