Re: [PATCH] pinctrl: sunxi: A523: fix voltage withstand encoding

[Chen-Yu Tsai]

On Fri, Jul 31, 2026 at 10:08 PM Andre Przywara <andre.przywara@xxxxxxx> wrote:
>
> Hi Juan,
>
> On 7/30/26 19:40, Juan Manuel wrote:
> > Hi Andre,
> >
> >> There is more to enabling Ethernet on the box, though, right? The
> >> EMAC25M pin needs to be configured correctly - not even sure that
> >> works cleanly with mainline? And what are the delay values that work
> >> for you?
> >
> > Right, the withstand fix alone isn't enough. Three things were needed to
> > get GMAC1 up on the OPi 4A:
>
> Sorry, there might be some confusion here: I think Chen-Yu already
> mentioned that Ethernet works on his OPi 4A, with just the withstanding fix.
> I think I was mixing this up with the X96QPro+ TV box when asking, which
> also uses the second MAC, but has a different setup.
> So are you talking about the Orange Pi 4A? Because ...

I only said the patch fixes eMMC. Ethernet already worked before. Though
to be honest, ethernet on the A523 has other problems. The performance
is really bad (even RX), and there are errors or packet drops.

ChenYu

> > 1) The PJ pinmux. Mainline's rgmii1 group was missing PJ10, which left
> >     one RX signal unmapped, so I got rx_packets=0. The BSP muxes the full
> >     PJ0..PJ15 (16 pins) as function "gmac1" (mux 5); with all 16 mapped,
> >     RX comes alive. I don't mux any separate/dedicated 25 MHz clock-out
> >     pin beyond that gmac1 group, and the link is rock solid, so on this
> >     board the PHY's 25 MHz reference isn't provided by an extra SoC pin.
>
> I think there is some misunderstanding here, probably caused by
> Allwinner's naming of that pin. Pin PJ10 (and PH13, inside the GMAC0
> group) are mere clock fanouts, they connect internally to two gated
> divider clocks, with the main peripheral PLL as their parent. They
> produce a 25 MHz clock signal, which is simply routed out to those pins.
> They work independently of the MACs, and could be even used for
> something else.
>
> On boards which do not use a crystal oscillator to clock the PHY (most
> boards, including the OPi 4A, have an oscillator!), the pin is not
> needed, hence we didn't include it in the pinmux. According to the
> schematic, PJ10 is not even connected on the OPi 4A, so whether you
> include it in the pinmux or not doesn't matter.
>
> So can you please double check this? For PJ10 to have any effect, it
> also would need the associated clock enabled.
>
> And for the records: I think I found now the proper solution to enable
> Ethernet on the X96QPro+: the pinmux for PJ10 gets added, either in the
> PHY, or the MAC DT node. The associated EPHY_25M clock must then be
> referenced by the PHY node. And the respective PHY driver needs to
> enable that clock (some do, others don't).
> With those things in place, Ethernet works on the X96QPro+ board, which
> does not feature a crystal oscillator, hence relies on that 25 MHz clock
> output to step in.
>
> > 2) RGMII clock delays. The board has a Motorcomm YT8531 PHY:
> >       - phy-mode          = "rgmii-rxid"
> >       - PHY node          : rx-internal-delay-ps = 1900  (YT8531
> > RXC_DLY_EN, ~1.9ns)
> >       - MAC syscon        : tx-internal-delay-ps = 100
> >                             rx-internal-delay-ps = 0
> >     That combo gives a stable 1 Gbps / full-duplex link, 0% packet loss.
>
> Those settings differ from what's in mainline. What are the results with
> those delays? Does it work as well, and those are just other settings
> that happen to work, because the math works out the same?
>
> Cheers,
> Andre
>
> > 3) Your withstand encoding fix. Before it, the PJ bank was driven at 1.8V
> >     while the receiver sat in 3.3V mode, so RX was effectively deaf. With
> >     your patch RX reads correctly.
> >
> > All of the above is validated on my board (2026-07-08): link up at
> > 1 Gbps/full, ping 0% loss over a sustained transfer.
> >
> > Thanks again for the withstand fix - glad the POW_MOD_SEL patch helped
> > connect the dots.
> >
> > Cheers,
> > Juan
>