Re: [PATCH 1/7] x86/sev: Add support for Alternate Injection

[Tom Lendacky]

On 7/29/26 20:48, Melody Wang wrote:
> The Alternate Injection feature is a method to protect an AMD
> confidential computing guest from malicious injection attacks. It allows
> the guest to control the interrupt injection.
> 
> When this feature is enabled, interrupts are injected with the help of
> an agent called a Secure VM Service Module (SVSM) which executes in the
> security realm of the guest and uses Restricted Injection as the sole
> method to receive interrupts from the hypervisor.
> 
> Add support for Alternate Injection enablement.

But you haven't added any support for it here. You've added a Kconfig
option (do we really need it?) that is unused and renamed the ALT_INJ bit
to ALTERNATE_INJ, which introduces a lot of churn.

I don't think the rename is needed, but if you really want to do it then
it should be a patch on its own.

And only introduce the Kconfig option when you're going to actually use it.

Thanks,
Tom

> 
> Signed-off-by: Melody Wang <huibo.wang@xxxxxxx>
> ---
>  arch/x86/Kconfig                   | 14 ++++++++++++++
>  arch/x86/boot/compressed/sev.c     |  2 +-
>  arch/x86/coco/core.c               |  3 +++
>  arch/x86/coco/sev/core.c           |  2 +-
>  arch/x86/include/asm/cpufeatures.h |  1 +
>  arch/x86/include/asm/msr-index.h   |  4 ++--
>  include/linux/cc_platform.h        |  8 ++++++++
>  7 files changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index e725b439d0a2..7ec5d2c4a8f0 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -493,6 +493,20 @@ config AMD_SECURE_AVIC
>  
>  	  If you don't know what to do here, say N.
>  
> +config AMD_ALTERNATE_INJ
> +	bool "Support Alternate Injection"
> +	depends on X86_X2APIC && AMD_MEM_ENCRYPT
> +	help
> +	  Enable AMD Alternate Injection support for SNP guests.
> +
> +	  The Alternate Injection feature of SEV-SNP enhances the security of
> +	  a confidential VM by preventing the untrusted host from presenting
> +	  unexpected interrupts or exceptions, while still preserving the
> +	  standard interrupt dispatch semantics inherent to the x86
> +	  architecture.
> +
> +	  If you don't know what to do here, say N.
> +
>  config X86_POSTED_MSI
>  	bool "Enable MSI and MSI-x delivery by posted interrupts"
>  	depends on X86_64 && IRQ_REMAP
> diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c
> index c6512f2ea31e..fc2029746c50 100644
> --- a/arch/x86/boot/compressed/sev.c
> +++ b/arch/x86/boot/compressed/sev.c
> @@ -179,7 +179,7 @@ bool sev_es_check_ghcb_fault(unsigned long address)
>  #define SNP_FEATURES_IMPL_REQ	(MSR_AMD64_SNP_VTOM |			\
>  				 MSR_AMD64_SNP_REFLECT_VC |		\
>  				 MSR_AMD64_SNP_RESTRICTED_INJ |		\
> -				 MSR_AMD64_SNP_ALT_INJ |		\
> +				 MSR_AMD64_SNP_ALTERNATE_INJ |		\
>  				 MSR_AMD64_SNP_DEBUG_SWAP |		\
>  				 MSR_AMD64_SNP_VMPL_SSS |		\
>  				 MSR_AMD64_SNP_SECURE_TSC |		\
> diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c
> index 989ca9f72ba3..aabda3ddc0e2 100644
> --- a/arch/x86/coco/core.c
> +++ b/arch/x86/coco/core.c
> @@ -107,6 +107,9 @@ static bool noinstr amd_cc_platform_has(enum cc_attr attr)
>  	case CC_ATTR_SNP_SECURE_AVIC:
>  		return sev_status & MSR_AMD64_SNP_SECURE_AVIC;
>  
> +	case CC_ATTR_SNP_ALTERNATE_INJECTION:
> +		return sev_status & MSR_AMD64_SNP_ALTERNATE_INJ;
> +
>  	default:
>  		return false;
>  	}
> diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c
> index ecd77d3217f3..197119807230 100644
> --- a/arch/x86/coco/sev/core.c
> +++ b/arch/x86/coco/sev/core.c
> @@ -78,7 +78,7 @@ static const char * const sev_status_feat_names[] = {
>  	[MSR_AMD64_SNP_VTOM_BIT]		= "vTom",
>  	[MSR_AMD64_SNP_REFLECT_VC_BIT]		= "ReflectVC",
>  	[MSR_AMD64_SNP_RESTRICTED_INJ_BIT]	= "RI",
> -	[MSR_AMD64_SNP_ALT_INJ_BIT]		= "AI",
> +	[MSR_AMD64_SNP_ALTERNATE_INJ_BIT]	= "AI",
>  	[MSR_AMD64_SNP_DEBUG_SWAP_BIT]		= "DebugSwap",
>  	[MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT]	= "NoHostIBS",
>  	[MSR_AMD64_SNP_BTB_ISOLATION_BIT]	= "BTBIsol",
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 3d0940a3b9f3..70dedbf0969f 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -454,6 +454,7 @@
>  #define X86_FEATURE_SNP_SECURE_TSC	(19*32+ 8) /* SEV-SNP Secure TSC */
>  #define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* Virtual TSC_AUX */
>  #define X86_FEATURE_SME_COHERENT	(19*32+10) /* hardware-enforced cache coherency */
> +#define X86_FEATURE_ALTERNATE_INJECTION	(19*32+13) /* SEV Alternate Injection */
>  #define X86_FEATURE_DEBUG_SWAP		(19*32+14) /* "debug_swap" SEV-ES full debug state swap support */
>  #define X86_FEATURE_RMPREAD		(19*32+21) /* RMPREAD instruction */
>  #define X86_FEATURE_SEGMENTED_RMP	(19*32+23) /* Segmented RMP support */
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 18c4be75e927..e4eab2210518 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -721,8 +721,8 @@
>  #define MSR_AMD64_SNP_REFLECT_VC	BIT_ULL(MSR_AMD64_SNP_REFLECT_VC_BIT)
>  #define MSR_AMD64_SNP_RESTRICTED_INJ_BIT 5
>  #define MSR_AMD64_SNP_RESTRICTED_INJ	BIT_ULL(MSR_AMD64_SNP_RESTRICTED_INJ_BIT)
> -#define MSR_AMD64_SNP_ALT_INJ_BIT	6
> -#define MSR_AMD64_SNP_ALT_INJ		BIT_ULL(MSR_AMD64_SNP_ALT_INJ_BIT)
> +#define MSR_AMD64_SNP_ALTERNATE_INJ_BIT	6
> +#define MSR_AMD64_SNP_ALTERNATE_INJ	BIT_ULL(MSR_AMD64_SNP_ALTERNATE_INJ_BIT)
>  #define MSR_AMD64_SNP_DEBUG_SWAP_BIT	7
>  #define MSR_AMD64_SNP_DEBUG_SWAP	BIT_ULL(MSR_AMD64_SNP_DEBUG_SWAP_BIT)
>  #define MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT 8
> diff --git a/include/linux/cc_platform.h b/include/linux/cc_platform.h
> index 559353ad64ac..90ef67e85cd3 100644
> --- a/include/linux/cc_platform.h
> +++ b/include/linux/cc_platform.h
> @@ -104,6 +104,14 @@ enum cc_attr {
>  	 * to run SEV-SNP guests with full Secure AVIC capabilities.
>  	 */
>  	CC_ATTR_SNP_SECURE_AVIC,
> +
> +	/**
> +	 * @CC_ATTR_SNP_ALTERNATE_INJECTION: AMD Alternate Injection enabled on the host.
> +	 *
> +	 * The host kernel is running with the necessary features
> +	 * needed to run Alternate Injection enabled guests.
> +	 */
> +	CC_ATTR_SNP_ALTERNATE_INJECTION,
>  };
>  
>  #ifdef CONFIG_ARCH_HAS_CC_PLATFORM