[PATCH 6/7] arm64: dts: qcom: glymur: Add ADC support for Glymur CRD
From: Jishnu Prakash
Date: Fri Jul 31 2026 - 14:17:57 EST
Add the ADC channels under the PMK8850 ADC node for the
other PMICS on the board with ADC peripherals. This includes
die temperature and VPH power channels per PMIC.
Add a thermal zone corresponding to the PMK8850 xo_therm
ADC thermistor channel to enable temperature monitoring.
Also add io-channels and io-channel-names properties to the
temp_alarm nodes so that they can get temperature reading
from the newly added ADC die_temp channels.
Signed-off-by: Jishnu Prakash <jishnu.prakash@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 143 +++++++++++++++++++++++++++++++
1 file changed, 143 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
index e784b538f42e..1487864482f8 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi
@@ -11,6 +11,7 @@
#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */
#include <dt-bindings/input/gpio-keys.h>
+#include "qcom-adc5-gen4.h"
/ {
model = "Qualcomm Technologies, Inc. Glymur CRD";
@@ -68,6 +69,26 @@ switch-lid {
};
};
+ thermal-zones {
+ sys-0-thermal {
+ thermal-sensors = <&pmk8850_vadc ADC5_GEN4_AMUX1_THM_100K_PU(0, 0)>;
+
+ trips {
+ trip0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ trip1 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+ };
+
vreg_nvme: regulator-nvme {
compatible = "regulator-fixed";
@@ -537,6 +558,26 @@ &pcie6_port0 {
wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
};
+&pmcx0102_c_e0_temp_alarm {
+ io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 2)>;
+ io-channel-names = "thermal";
+};
+
+&pmcx0102_c_e1_temp_alarm {
+ io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(1, 2)>;
+ io-channel-names = "thermal";
+};
+
+&pmcx0102_d_e0_temp_alarm {
+ io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 3)>;
+ io-channel-names = "thermal";
+};
+
+&pmcx0102_d_e1_temp_alarm {
+ io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(1, 3)>;
+ io-channel-names = "thermal";
+};
+
&pmh0101_gpios {
nvme_reg_en: nvme-reg-en-state {
pins = "gpio14";
@@ -545,6 +586,11 @@ nvme_reg_en: nvme-reg-en-state {
};
};
+&pmh0101_temp_alarm {
+ io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 1)>;
+ io-channel-names = "thermal";
+};
+
&pmh0110_f_e1_gpios {
nvme_sec_reg_en: nvme-reg-en-state {
pins = "gpio14";
@@ -562,10 +608,107 @@ key_vol_up_default: key-vol-up-default-state {
};
};
+&pmh0110_f_e0_temp_alarm {
+ io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 5)>;
+ io-channel-names = "thermal";
+};
+
+&pmh0110_f_e1_temp_alarm {
+ io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(1, 5)>;
+ io-channel-names = "thermal";
+};
+
+&pmh0110_h_e0_temp_alarm {
+ io-channels = <&pmk8850_vadc ADC5_GEN4_DIE_TEMP(0, 7)>;
+ io-channel-names = "thermal";
+};
+
&pmk8850_rtc {
qcom,no-alarm;
};
+&pmk8850_vadc {
+ channel@103 {
+ reg = <ADC5_GEN4_DIE_TEMP(0, 1)>;
+ label = "pmh0101_die_temp";
+ };
+
+ channel@18e {
+ reg = <ADC5_GEN4_VPH_PWR(0, 1)>;
+ label = "pmh0101_vph_pwr";
+ };
+
+ channel@203 {
+ reg = <ADC5_GEN4_DIE_TEMP(0, 2)>;
+ label = "pmcx0102_c_e0_die_temp";
+ };
+
+ channel@28e {
+ reg = <ADC5_GEN4_VPH_PWR(0, 2)>;
+ label = "pmcx0102_c_e0_vph_pwr";
+ };
+
+ channel@303 {
+ reg = <ADC5_GEN4_DIE_TEMP(0, 3)>;
+ label = "pmcx0102_d_e0_die_temp";
+ };
+
+ channel@38e {
+ reg = <ADC5_GEN4_VPH_PWR(0, 3)>;
+ label = "pmcx0102_d_e0_vph_pwr";
+ };
+
+ channel@503 {
+ reg = <ADC5_GEN4_DIE_TEMP(0, 5)>;
+ label = "pmh0110_f_e0_die_temp";
+ };
+
+ channel@58e {
+ reg = <ADC5_GEN4_VPH_PWR(0, 5)>;
+ label = "pmh0110_f_e0_vph_pwr";
+ };
+
+ channel@703 {
+ reg = <ADC5_GEN4_DIE_TEMP(0, 7)>;
+ label = "pmh0110_h_e0_die_temp";
+ };
+
+ channel@78e {
+ reg = <ADC5_GEN4_VPH_PWR(0, 7)>;
+ label = "pmh0110_h_e0_vph_pwr";
+ };
+
+ channel@2203 {
+ reg = <ADC5_GEN4_DIE_TEMP(1, 2)>;
+ label = "pmcx0102_c_e1_die_temp";
+ };
+
+ channel@228e {
+ reg = <ADC5_GEN4_VPH_PWR(1, 2)>;
+ label = "pmcx0102_c_e1_vph_pwr";
+ };
+
+ channel@2303 {
+ reg = <ADC5_GEN4_DIE_TEMP(1, 3)>;
+ label = "pmcx0102_d_e1_die_temp";
+ };
+
+ channel@238e {
+ reg = <ADC5_GEN4_VPH_PWR(1, 3)>;
+ label = "pmcx0102_d_e1_vph_pwr";
+ };
+
+ channel@2503 {
+ reg = <ADC5_GEN4_DIE_TEMP(1, 5)>;
+ label = "pmh0110_f_e1_die_temp";
+ };
+
+ channel@258e {
+ reg = <ADC5_GEN4_VPH_PWR(1, 5)>;
+ label = "pmh0110_f_e1_vph_pwr";
+ };
+};
+
&pon_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
--
2.43.0