Re: [PATCH v2 2/6] perf mem: Add support for printing PERF_MEM_LVLNUM_L0

[Namhyung Kim]

On Thu, Jul 30, 2026 at 01:46:27PM +0800, Mi, Dapeng wrote:
> 
> On 7/29/2026 1:13 AM, Namhyung Kim wrote:
> > Hello,
> >
> > On Mon, Jul 13, 2026 at 07:43:55PM -0500, Thomas Falcon wrote:
> >> From: Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx>
> >>
> >> Add support for printing PERF_MEM_LVLNUM_L0 in perf mem report.
> > What's the L0, by the way?
> 
> Per my understanding, the L0 cache is newly added a small piece of cache
> which is the closest, lowest-latency memory cache tied directly to the
> execution pipeline. 
> 
> The table "Table 9-4. Data Source Field Encodings for Panther Cove and
> Coyote Cove Microarchitectures" in the ISE doc chapter "9.2.1 Panther Cove
> and Coyote Cove Microarchitectures Memory Auxiliary Field Layout" indicates
> the code "01H" means the "L0 Hit - Minimal latency core cache hit. This
> request was satisfied by the L0 data cache."
> 
> https://www.intel.com/content/www/us/en/content-details/922690/intel-architecture-instruction-set-extensions-programming-reference.html ;

Interesting, thanks for the explanation!

Thanks,
Namhyung