[PATCH v3 0/5] Initial device tree support for StarFive JHB100 SoC

[Changhuang Liang]

StarFive JHB100 SoC consists of 4 RISC-V low power Cores (Dubhe-70). It
also features various interfaces such as I2C, SPI, CAN, USB, MMC, Uart,
etc.

This patch series introduces initial SoC DTSI support for the StarFive
JHB100 SoC. The relevant dt-binding documentation has been updated
accordingly. Below is the list of IP blocks added in the initial SoC DTSI.

- StarFive Dubhe-70 CPU
- PMU
- PLIC
- CLINT
- UART
- INTC

changes since v2:
- Add a new patch 4

patch 5:
- Remove the 'riscv,isa' property.
- Add 'starfive,jhb100-uart' to the UART node.
- Update bus node name.
- Remove the interrupts-extended property in riscv,pmu

v2: https://lore.kernel.org/all/20260506085937.754808-1-changhuang.liang@xxxxxxxxxxxxxxxx/
v1: https://lore.kernel.org/all/20260402084019.440708-1-changhuang.liang@xxxxxxxxxxxxxxxx/

Changhuang Liang (1):
  dt-bindings: serial: snps-dw-apb-uart: Add StarFive JHB100 UART
    compatible

Ji Sheng Teoh (1):
  dt-bindings: riscv: Add StarFive Dubhe-70 compatibles

Ley Foon Tan (3):
  dt-bindings: interrupt-controller: Add StarFive JHB100 plic
  dt-bindings: riscv: Add StarFive JHB100 SoC
  riscv: dts: starfive: jhb100: Add JHB100 base DT

 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../devicetree/bindings/riscv/cpus.yaml       |   1 +
 .../devicetree/bindings/riscv/starfive.yaml   |   5 +
 .../bindings/serial/snps-dw-apb-uart.yaml     |   1 +
 MAINTAINERS                                   |   6 +
 arch/riscv/boot/dts/starfive/Makefile         |   2 +
 arch/riscv/boot/dts/starfive/jhb100-evb1.dts  |  32 ++
 arch/riscv/boot/dts/starfive/jhb100.dtsi      | 331 ++++++++++++++++++
 8 files changed, 379 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi

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2.25.1