Re: [PATCH] pinctrl: airoha: fix wrong value for PCIe reset pin

[Linus Walleij]

Hi Christian,

On Wed, Aug 5, 2026 at 10:41 AM Christian Marangi <ansuelsmth@xxxxxxxxx> wrote:

> The PCIe reset pin actually require the bit to be set as 0 to work as PCIe
> reset pin. When the bit is set as 1, then the PCIe reset pin act as a GPIO
> for GPIO44, GPIO45 and GPIO46.
>
> Cc: stable@xxxxxxxxxxxxxxx
> Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
> Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx>

Is this already fixed in the big Airoha patch set from Mikhail
that I just applied?

If this is *not* fixed in what is currently in my tree I need
a rebased version of this for mainline.

If it *is* fixed in what is currently in my tree, this can be
sent separately to the stable tree as a backport once
Torvalds has pulled my changes.

Yours,
Linus Walleij