Re: [PATCH v2 5/9] clk: renesas: rzg2l: Add support for LVDS fixed-factor divider with 4:7 duty cycle

[Geert Uytterhoeven]

Hi Biju,

On Tue, 11 Aug 2026 at 20:27, Biju <biju.das.au@xxxxxxxxx> wrote:
>
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Add a new CLK_TYPE_G3L_LVDS_DIV clock type and register function for
> a fixed-factor divider used by the LVDS clock, which cannot produce a
> 50% duty cycle for odd divider values. Implement a custom
> get_duty_cycle() callback that reports the actual (div + 1) / 2 : div
> duty cycle, and add the DEF_G3L_LVDS_DIV() macro to define such
> clocks.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Thanks for your patch!

> +static int rzg3l_cpg_lvds_div_get_duty_cycle(struct clk_hw *hw,
> +                                            struct clk_duty *duty)
> +{
> +       struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
> +
> +       /*
> +        * An odd divider cannot generate a 50% duty cycle: the output stays
> +        * high for (div + 1) / 2 input clock cycles out of div, e.g. a divider
> +        * of 7 gives a duty cycle of 4/7.
> +        */
> +       duty->num = (fix->div + 1) / 2;

DIV_ROUND_UP()

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v7.4, with the above fixed.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

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