[PATCH 1/2] PCI: Add MMIO Capabilities Register Block definitions
From: peng.guo
Date: Sun Aug 16 2026 - 05:05:55 EST
From: pguo <peng.guo@xxxxxxxxxxxxxxxx>
The PCIe Management Message Passthrough via MMIO Mailbox ECN defines
the MMIO Capabilities Register Block (MCAP). MCAP contains an array
header followed by capability headers that describe the ID, version,
location, size, and vendor of each MMIO capability.
Add definitions for the MCAP array and capability headers so that
subsystem drivers can distinguish capabilities with overlapping IDs
by using the Vendor ID field.
Signed-off-by: pguo <peng.guo@xxxxxxxxxxxxxxxx>
---
include/uapi/linux/pci_regs.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 14f634ab9350..5fe6bc711526 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1338,6 +1338,27 @@
#define PCI_IDE_SEL_ADDR_3(x) (28 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE)
#define PCI_IDE_SEL_BLOCK_SIZE(nr_assoc) (20 + PCI_IDE_SEL_ADDR_BLOCK_SIZE * (nr_assoc))
+/* MMIO Capabilities Register Block (MCAP) */
+#define PCI_MCAP_ARRAY_1 0x00
+#define PCI_MCAP_ARRAY_ID __GENMASK(15, 0)
+#define PCI_MCAP_ARRAY_VERSION __GENMASK(23, 16)
+#define PCI_MCAP_ARRAY_TYPE __GENMASK(27, 24)
+#define PCI_MCAP_ARRAY_TYPE_CLASS_CODE 0x0
+#define PCI_MCAP_ARRAY_2 0x04
+#define PCI_MCAP_ARRAY_COUNT __GENMASK(15, 0)
+
+#define PCI_MCAP_HDR_SIZEOF 0x10
+#define PCI_MCAP_HDR_BASE(n) ((n) * PCI_MCAP_HDR_SIZEOF)
+#define PCI_MCAP_HDR_REG_1 0x00
+#define PCI_MCAP_CAP_ID __GENMASK(15, 0)
+#define PCI_MCAP_CAP_VERSION __GENMASK(23, 16)
+#define PCI_MCAP_HDR_REG_2 0x04
+#define PCI_MCAP_HDR_OFFSET __GENMASK(31, 0)
+#define PCI_MCAP_HDR_REG_3 0x08
+#define PCI_MCAP_HDR_LENGTH __GENMASK(31, 0)
+#define PCI_MCAP_HDR_REG_4 0x0c
+#define PCI_MCAP_HDR_VENDOR_ID __GENMASK(15, 0)
+
/*
* Compute Express Link (CXL r4.0, sec 8.1)
*
--
2.43.0