Re: [BUG] x86/tsc: ~1 second TSC skew when bringing a secondary CPU online on Ryzen 7 8840HS

[Thomas Gleixner]

On Sat, Aug 15 2026 at 20:17, David Kostial wrote:
>   smpboot: Booting Node 0 Processor 1 APIC 0x1
>   TSC synchronization [CPU#0 -> CPU#1]:
>   Measured 3360957369 cycles TSC warp between CPUs, turning off TSC clock.
>   tsc: Marking TSC unstable due to check_tsc_sync_source failed
>   TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'.
>   clocksource: Switched to clocksource hpet
....
> I'm not sure whether the root cause is firmware/AGESA or whether there
> is anything x86/tsc should handle differently here.

That's a firmware problem. The firmware messes up the TSC synchronization.

The kernel can't do anything about this as the CPU does not have the
TSC_ADJUST MSR.

We tried to write to the TSC MSR directly, but that turned out to be
fragile and unreliable so we restricted the fixup attempts to CPUs which
have the TSC_ADJUST MSR.

Thanks,

        tglx