[PATCH 2/2] arm64: dts: exynos: Add initial support for Samsung Galaxy Watch FE
From: Aiden Isik via B4 Relay
Date: Mon Aug 17 2026 - 06:27:55 EST
From: Aiden Isik <aidenisik@xxxxxxxxxxxxxx>
The Samsung Galaxy Watch FE (SM-R861/SM-R866), codenamed lucky7, is a
smartwatch developed by Samsung and released in 2024. It has 1.5GiB RAM,
16GiB of eMMC storage, an Exynos5515 (W920) SoC, and a 396x396 display.
Support for the following is added by this device tree:
- Bootloader framebuffer
- Memory
Only the lowest 490MiB and highest 512MiB of memory are used for now.
The 488MiB between the addresses of 0x9ea00000 and 0xbe680000 is excluded
from the memory node due to a bug where if the kernel even knows about
the existence of this memory, one or both cores will lock up and cause
an RCU stall.
Signed-off-by: Aiden Isik <aidenisik+git@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts | 106 +++++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts b/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts
new file mode 100644
index 000000000000..f91ea7e44cf8
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5515-lucky7.dts
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Samsung Galaxy Watch FE (lucky7/SM-R861/SM-R866) device tree source
+ *
+ * Copyright (c) 2026 Aiden Isik <aidenisik+git@xxxxxxxxxxxxxx>
+ */
+
+/dts-v1/;
+#include "exynos5515.dtsi"
+
+/ {
+ compatible = "samsung,lucky7", "samsung,exynos5515";
+ chassis-type = "watch";
+ model = "Samsung Galaxy Watch FE (SM-R861/SM-R866)";
+
+ chosen {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ framebuffer@9e0cf000 {
+ compatible = "simple-framebuffer";
+ reg = <0x0 0x9e0cf000 (396 * 396 * 4)>;
+ format = "a8r8g8b8";
+ height = <396>;
+ stride = <(396 * 4)>;
+ width = <396>;
+ };
+ };
+
+ memory@80000000 {
+ /*
+ * Use the lowest 490MiB and highest 512MiB of memory.
+ * The 488MiB between the addresses of 0x9ea00000 and
+ * 0xbe680000 is currently unused due to any memory accesses
+ * in several ranges between those addresses causing the core
+ * performing the accesses to stall.
+ */
+ reg = <0x0 0x80000000 0x1ea00000>,
+ /* Crashing memory at 0x9ea00000-0xbe680000 */
+ /* Memory hole at 0xbe680000-0xc0000000 */
+ <0x0 0xc0000000 0x20000000>;
+ device_type = "memory";
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ framebuffer@9e0cf000 {
+ reg = <0x0 0x9e0cf000 (396 * 396 * 4)>;
+ no-map;
+ };
+
+ misc-rmem {
+ /*
+ * Some of these regions belong to memory-mapped
+ * devices, and will be assigned to drivers as support
+ * is added.
+ *
+ * Other regions belong to the TrustZone firmware
+ * and should never be touched.
+ */
+ reg = <0x0 0x87000000 0x200000>,
+ <0x0 0x87fff000 0x1000>,
+ <0x0 0x8a000000 0x31000>,
+ <0x0 0x8d800000 0x180000>,
+ <0x0 0x8ffff000 0x33000>,
+ <0x0 0x90100000 0x200000>,
+ <0x0 0x98a00000 0x600000>,
+ <0x0 0x9a000000 0xc00000>,
+ <0x0 0x9b000000 0x400000>,
+ <0x0 0x9bd00000 0x208000>,
+ <0x0 0x9c000000 0x20000>,
+ <0x0 0xa0000000 0x10000>,
+ <0x0 0xa0010000 0x400000>,
+ <0x0 0xa0510000 0x1000>,
+ <0x0 0xa0900000 0x2000>,
+ <0x0 0xa0902000 0x1000>,
+ <0x0 0xa0910000 0x3c000>,
+ <0x0 0xb0000000 0x200000>,
+ <0x0 0xb1000000 0x200000>,
+ <0x0 0xbbfff000 0x1000000>,
+ <0x0 0xbcfff000 0x1000>,
+ <0x0 0xbd430000 0x1250000>,
+ <0x0 0xd0000000 0x5d00000>,
+ <0x0 0xdc444000 0x2bbc000>,
+ <0x0 0xdf005000 0x1000>,
+ <0x0 0xdf008000 0x1000>,
+ <0x0 0xdf009000 0x12000>,
+ <0x0 0xdf01b000 0x21000>,
+ <0x0 0xdf03c000 0x1000>,
+ <0x0 0xdf03d000 0xfc3000>;
+ no-map;
+ };
+ };
+};
+
+&oscclk {
+ clock-frequency = <26000000>;
+};
+
+&watchdog {
+ status = "okay";
+};
--
2.54.0