RE: [PATCH 2/3] clk: samsung: clk-pll: Add support for pll_309

[Alim Akhtar]

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> From: Aiden Isik via B4 Relay
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> Sent: Monday, August 17, 2026 3:47 PM
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> <s.nawrocki@xxxxxxxxxxx>; Chanwoo Choi <cw00.choi@xxxxxxxxxxx>;
> Peter Griffin <peter.griffin@xxxxxxxxxx>; Alim Akhtar
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> Subject: [PATCH 2/3] clk: samsung: clk-pll: Add support for pll_309
> 
> From: Aiden Isik <aidenisik@xxxxxxxxxxxxxx>
> 
> pll_309 (referred to in the downstream kernel sources as frd_309_rpll) is one
> of two PLLs used in the Exynos5515 SoC. It is an integer/fractional PLL with an
> FVCO of 600-2400MHz.
> 
> It has the same locktime (500), and kdiv/mdiv/pdiv/sdiv masks and shifts as
> pll_531x, so it can be handled in exactly the same way.
> 
> When defining a PLL, the "con" parameter should be set to the CON3 register,
> like this:
> 
> PLL(pll_309, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
>     PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL),
> 
This patch does more then what is described above; please explain all changes in the commit. 
If needed, split this into common and pll_309 specific changes. Thanks!

Regards,
Alim