Re: [PATCH v5 1/2] dt-bindings: clock: qcom: Add LPASS VA CSR HeartBeat pulse clock

[Konrad Dybcio]

On 8/10/26 6:01 PM, Bjorn Andersson wrote:
> On Thu, Aug 06, 2026 at 08:21:36PM +0530, Sarath Ganapathiraju via B4 Relay wrote:
>> From: Sarath Ganapathiraju <sarath.ganapathiraju@xxxxxxxxxxxxxxxx>
>>
>> Add a binding for the Qualcomm LPASS VA CSR rate generator node that
>> exposes the lpass_heartbeat_pulse clock on hawi.

[...]

>> +examples:
>> +  - |
>> +    soc {
>> +      #address-cells = <2>;
>> +      #size-cells = <2>;
>> +
>> +      clock-controller@7eed000 {
>> +        compatible = "qcom,hawi-lpass-va-csr";
>> +        reg = <0x0 0x07eed000 0x0 0x14>;
> 
> The two 0x0 cells are just there in the normal dtsi because we need
> address- and size-cells of 2. But you don't need that in your example.
> 
> If you change this to <0x07eed000 0x14> you can drop the
> address/size-cells and the whole soc {} level from the example.
> 
> 
> That said, is this really a 20 byte large IP-block? Or is this part of
> some larger function? Will we have overlapping/conflicting mappings of
> this block?

I raised a similar concern, but it seems my concern was misunderstood

https://lore.kernel.org/linux-arm-msm/20260804110714.2951829-1-sarath.ganapathiraju@xxxxxxxxxxxxxxxx/

I think we should still cover the full register space

Konrad