[PATCH 0/2] EDAC/ie31200: Fix multi-controller error capture, add Arrow Lake-S

[Emba Consulting]

The ie31200 driver has handled two integrated memory controllers since
Raptor Lake-S, but it still reads and clears error state one controller at
a time. ERRSTS lives in the shared host bridge and clearing it drops the
logs of every controller, so servicing mc0 can discard an error mc1 has
latched and not yet reported. The MSR clear path has the same problem.

Patch 1 fixes that: snapshot every configured controller and channel
first, clear once, then dispatch each log to the controller that owns it.
Patch 2 is Johan's Arrow Lake-S enablement on top. It needs patch 1
because Arrow Lake-S is the first configuration to combine two
controllers with CMCI disabled, which is what puts the polling path on
this code.

Tooling disclosure: the ordering bug was found by tool-assisted source
analysis and the patch 1 diff as posted is that tool's output unchanged.
I rewrote its changelog by hand, reviewed the diff line by line and take
responsibility for it; patch 1 carries the matching Assisted-by tags.
Patch 2 is Johan's own work.

Testing:

Johan ran the pair on an ASRock W880M WS with a Core Ultra 5 245K (host
bridge 7d2a). Both controllers register and are reported as polled, the
DIMM geometry decodes correctly against his 2x16 GiB DDR5 population, idle
counters stayed flat across several poll intervals, and an unload/reload
cycle reproduced the same topology. He has no corrected-error injection
method on that board, so the capture-and-dispatch path is not validated
against a real CE yet. That is the gap I would most like a second pair of
eyes on.

His hardware run was on 7.1.7 with patch 2 context-adapted for that tree.
The Arrow Lake-S configuration and PCI IDs are identical to patch 2 here;
only the surrounding table formatting differs, which is why his Tested-by
is on patch 1.

Here I have source-side coverage only: strict checkpatch, GCC W=1, Sparse
C=2 and an allmodconfig-derived build on this base, plus a W=1 build of
patch 1 on 7.1.7. I have not loaded the module on my own machines and I
have injected no errors.

Patch 1 carries a Fixes: tag. What is reachable today is the MSR path: the
Raptor Lake-S config is bound to 20 host bridge IDs (RPL-S, RPL-HX, ADL-S,
BTL-S) with two controllers and CMCI enabled, so mce_check() walks both of
them and the package-wide MSR clear done for mc0 discards anything mc1 had
latched. The shared-ERRSTS variant only becomes reachable with patch 2,
which adds the first two-controller config with CMCI disabled. I have not
added a stable Cc because patch 2 does not apply to older trees unchanged;
backport scope for patch 1 alone is your call.

One unrelated thing Johan hit while testing: rmmod warns "Device '(null)'
does not have a release() function" once per registered controller, and
taints. ie31200_register_mci() calls device_initialize() on priv->dev but
never sets a release callback, so the put_device() in
ie31200_unregister_mcis() lands in device_release() with no release
method. Since both calls are unconditional this affects single-controller
parts too, not just the two-controller configs. It predates this series
and a separate patch will follow.

Emba (1):
  EDAC/ie31200: Capture all memory controllers before clearing errors

Johan Bergström (1):
  EDAC/ie31200: Add Intel Arrow Lake-S (Core Ultra 200S) support

 drivers/edac/ie31200_edac.c | 207 +++++++++++++++++++++++++++---------
 1 file changed, 158 insertions(+), 49 deletions(-)

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