[PATCH] arm64: dts: rockchip: fix an error and a typo in the CM5-IO comment

[Jiaxing Hu]

Two mistakes in the CM5-IO header comment.

The USB-C line names combphy0, but combphy0 is the M.2 PCIe lane, as the
comment above &combphy0_ps says. The USB-C SuperSpeed path is the USBDP
PHY.

The USB-A count is also wrong: the carrier has four ports, not two. The
RTS5411S USB 3.0 hub fans the single USB3 lane out to four downstream
USB-A ports.

Comment only, no functional change.

Signed-off-by: Jiaxing Hu <gahing@xxxxxxxxxxxxx>
---
 arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts
index ebb231271..335963227 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts
@@ -5,8 +5,8 @@
  * Carrier provides:
  *   - Full-size HDMI 2.1 (HDMI TX via HDPTX PHY)
  *   - Gigabit Ethernet RJ45 (GMAC0 + on-module YT8531)
- *   - 2x USB-A behind a USB3 hub (combphy1 + u2phy1)
- *   - USB-C with PD/altmode (FUSB302 on i2c0, combphy0 + USBDP PHY)
+ *   - 4x USB-A behind a USB3 hub (combphy1 + u2phy1)
+ *   - USB-C with PD/altmode (FUSB302 on i2c0, USBDP PHY)
  *   - M.2 PCIe 2.0 x1 slot (combphy0 as PCIe lane)
  *   - microSD card slot
  *   - Green/red status LEDs, 40-pin RPi-compatible header
-- 
2.43.0