Re: [PATCH v3 4/8] coresight: tmc-etr: Prevent per-thread events from sharing a sink

[Leo Yan]

On Fri, Aug 14, 2026 at 10:09:01AM +0100, James Clark wrote:

[...]

> There isn't any sharing with "another perf session", unless there is a
> mistake somewhere? Checking that the owners are equivalent enforces this. Or
> do you mean another event owned by the same process?

Now I understand that the problem is constrained to different events
within the same session.

> I'm not sure the exact model you had in mind was that still supports this
> and fixes the bugs?

Let me try to describe my understanding of the problem.

  ./perf test -w named_threads 2 1000000 &
  ./perf record -e cs_etm//u --per-thread --pid $!

We can simplify the flow as:

                | T1 |
  CPU0        ------------------------------
                   |   T2      |
  CPU1        ------------------------------
                               `> T2 stops and the driver reports
                                  the warning when trying to sync
                                  ETR_BUF(T1), while T2 is associated
                                  with ETR_BUF(T2).

  AUX_BUF(T1) |                            |
  ETR_BUF(T1) | Bounce buf0                |  -> Used by H/W trace


  AUX_BUF(T2) |                            |
  ETR_BUF(T2) | Bounce buf1                |  -> Not used by H/W trace

With `--per-thread --pid $PID`, perf creates separate events for the
child threads, say T1 and T2. Perf allocates a separate AUX buffer
for each event, and the ETR driver also allocates a separate bounce
buffer for each event. However, because there is only one shared ETR
sink, only one of those bounce buffers can actually be used by the
hardware at a time.

If T1 stops while T2 is still running, the ETR remains enabled. Later,
when T2 stops, the ETR is still using ETR_BUF(T1). This mismatch
triggers the warning and prevents the data from being copied.

I am just wandering if we can improve the sink driver to only allocate
a single bounce buffer that is independent of any threads (and any
associated events).

                | T1 |
  CPU0        ------------------------------
                   |   T2      |
  CPU1        ------------------------------
                               `> T2 stops and can sync trace
                                  from the shared bounce buffer
                                  to AUX_BUF(T2).

  AUX_BUF(T1) |                            |
  AUX_BUF(T2) |                            |

  ETR_BUF     | Bounce buf                 |  -> Used by H/W trace

This might also simplify the CPU-wide case. Each CPU would still have
its own AUX buffer, but the ETR driver would maintain only one bounce
buffer for the shared sink. A reference count could track how many
events are using the sink, with the final event responsible for
stopping the sink and copying the trace data from bounce buffer to aux
buffer.

> The one in this change is pretty complete and only does 4 comparisons,
> which seems quite simple to me.

Before going further with the heavily sink buffer refactoring, perhaps
a more pragmatic solution would be to reject the problematic case for
now. Can we do something like below?

+void coresight_trace_id_is_perf_started(struct coresight_trace_id_map *id_map)
+{
+	PERF_SESSION(atomic_read(&id_map->perf_cs_etm_session_active));
+}

@@ -399,6 +399,15 @@ etm_event_build_path(struct perf_event *event, int cpu,
 			goto out;
 	}
 
+	if (!coresight_trace_id_is_perf_started(&sink->perf_sink_id_map)) {
+		sink->perf_owner = event->owner;
+		sink->perf_target = event->hw.target;
+	} else {
+		if (sink->perf_owner != event->owner ||
+		    sink->perf_target != event->hw.target)
+			goto out;
+	}
+

We use a central place etm_event_build_path() to record and compare
event's owner and target process, then we don't need to spread the
check into sink drivers. We only care about if owner and target must
be consistent.

Regard of the inherit/inherit_thread, I always see they are consistent
within the same session. Should we ignore them?

Thanks,
Leo