[PATCH v3 4/4] arm64: dts: qcom: monaco{,-evk}: Move graph port/endpoint anchors to board file

[Wei Deng]

of_graph_is_present() only checks for the presence of a 'port' child
node, not whether remote-endpoint is actually connected. Adding empty
port anchor nodes to monaco.dtsi caused hci_qca to enter the M.2
pwrseq probe path on all monaco-based boards, including qcs8300-ride
which has a soldered WCN6855 and no M.2 Key E connector. This broke
BT initialization on qcs8300-ride.

Fix this by moving the port/endpoint nodes from monaco.dtsi into the
monaco-evk.dts board file where the M.2 connector is actually present,
so that of_graph_is_present() only returns true for boards that have
an M.2 Key E connector described.

Signed-off-by: Wei Deng <wei.deng@xxxxxxxxxxxxxxxx>
---
 arch/arm64/boot/dts/qcom/monaco-evk.dts | 16 ++++++++++------
 arch/arm64/boot/dts/qcom/monaco.dtsi    |  8 --------
 2 files changed, 10 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts
index 5930ddb3b4b1..5aae3d8c66a1 100644
--- a/arch/arm64/boot/dts/qcom/monaco-evk.dts
+++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts
@@ -688,10 +688,12 @@ &pcie1_phy {
 &pcieport0 {
 	reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
 	wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-};
 
-&pcieport0_ep {
-	remote-endpoint = <&m2_e_pcie_ep>;
+	port {
+		pcieport0_ep: endpoint {
+			remote-endpoint = <&m2_e_pcie_ep>;
+		};
+	};
 };
 
 &pcieport1 {
@@ -974,8 +976,10 @@ &usb_2_hsphy {
 
 &uart2 {
 	status = "okay";
-};
 
-&uart2_ep {
-	remote-endpoint = <&m2_e_uart_ep>;
+	port {
+		uart2_ep: endpoint {
+			remote-endpoint = <&m2_e_uart_ep>;
+		};
+	};
 };
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index b17d41059e7c..438ccf6eba64 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -1184,10 +1184,6 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 				power-domains = <&rpmhpd RPMHPD_CX>;
 				operating-points-v2 = <&qup_opp_table>;
 				status = "disabled";
-
-				port {
-					uart2_ep: endpoint {};
-				};
 			};
 
 			i2c3: i2c@98c000 {
@@ -2406,10 +2402,6 @@ pcieport0: pcie@0 {
 				#size-cells = <2>;
 				ranges;
 				phys = <&pcie0_phy>;
-
-				port {
-					pcieport0_ep: endpoint {};
-				};
 			};
 		};
 

-- 
2.34.1