[tip: irq/urgent] irqchip/gic-v5: Synchronize CPU interface disable

[tip-bot2 for Sascha Bischoff]

The following commit has been merged into the irq/urgent branch of tip:

Commit-ID:     ac6db0e0bee18cd4385418c752a007e1aba4ec14
Gitweb:        https://git.kernel.org/tip/ac6db0e0bee18cd4385418c752a007e1aba4ec14
Author:        Sascha Bischoff <Sascha.Bischoff@xxxxxxx>
AuthorDate:    Tue, 11 Aug 2026 15:27:31 
Committer:     Thomas Gleixner <tglx@xxxxxxxxxx>
CommitterDate: Thu, 20 Aug 2026 10:23:53 +02:00

irqchip/gic-v5: Synchronize CPU interface disable

The write disabling the GICv5 CPU interface is only guaranteed to take
effect after a context synchronization event. Without one, execution can
return from gicv5_cpu_disable_interrupts() while an interrupt is still
able to be taken.

Add an ISB after the ICC_CR0_EL1 write to ensure interrupts are
disabled before the function returns. No corresponding ISB is added
when enabling the interface, as interrupt delivery is asynchronous and
there is no obvious benefit to waiting for it.

Fixes: 7ec80fb3f025 ("irqchip/gic-v5: Add GICv5 PPI support")
Signed-off-by: Sascha Bischoff <sascha.bischoff@xxxxxxx>
Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxx>
Reviewed-by: Lorenzo Pieralisi <lpieralisi@xxxxxxxxxx>
Link: https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff@xxxxxxx?part=6
Link: https://patch.msgid.link/20260811152630.942023-3-sascha.bischoff@xxxxxxx
---
 drivers/irqchip/irq-gic-v5.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c
index 5dcf404..ca48c8b 100644
--- a/drivers/irqchip/irq-gic-v5.c
+++ b/drivers/irqchip/irq-gic-v5.c
@@ -983,6 +983,7 @@ static void gicv5_cpu_disable_interrupts(void)
 
 	cr0 = FIELD_PREP(ICC_CR0_EL1_EN, 0);
 	write_sysreg_s(cr0, SYS_ICC_CR0_EL1);
+	isb();
 }
 
 static void gicv5_cpu_enable_interrupts(void)