Re: [PATCH 06/12] arm64: assembler: Remove endianness helper macros

[Will Deacon]

On Sun, Aug 16, 2026 at 10:42:40AM +0100, Will Deacon wrote:
> On Tue, Aug 11, 2026 at 05:04:43PM +0200, Ard Biesheuvel wrote:
> > On Tue, 11 Aug 2026, at 16:01, Will Deacon wrote:
> > > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
> > > index 87a822e5c4ca..8951ce693552 100644
> > > --- a/arch/arm64/kernel/head.S
> > > +++ b/arch/arm64/kernel/head.S
> > > @@ -138,8 +138,7 @@ SYM_CODE_START_LOCAL(record_mmu_state)
> > >  	b.ne	0f
> > >  	mrs	x19, sctlr_el2
> > >  0:
> > > -CPU_LE( tbnz	x19, #SCTLR_ELx_EE_SHIFT, 1f	)
> > > -CPU_BE( tbz	x19, #SCTLR_ELx_EE_SHIFT, 1f	)
> > > +	tbnz	x19, #SCTLR_ELx_EE_SHIFT, 1f
> > >  	tst	x19, #SCTLR_ELx_C		// Z := (C == 0)
> > >  	and	x19, x19, #SCTLR_ELx_M		// isolate M bit
> > >  	csel	x19, xzr, x19, eq		// clear x19 if Z
> > 
> > There is some more code that can be removed here - see
> > 2ced0f30a426c7301350681f838344d5aea711e3
> 
> Good spot, thanks! I'll do some more surgery at -rc1.

Looking at this again, I'm not sure we can remove much here. I think we
probably still want to force little-endian (i.e. clear the EE bit) if
we're entered as big-endian. I've changed the following EOR to a BIC
(see below), but I think that's about all we can do?

Will

--->8

diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 8951ce693552..8dfb9db3722d 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -145,12 +145,12 @@ SYM_CODE_START_LOCAL(record_mmu_state)
        ret
 
        /*
-        * Set the correct endianness early so all memory accesses issued
-        * before init_kernel_el() occur in the correct byte order. Note that
-        * this means the MMU must be disabled, or the active ID map will end
-        * up getting interpreted with the wrong byte order.
+        * Force little-endian early so all memory accesses issued before
+        * init_kernel_el() occur in the correct byte order. Note that this
+        * means the MMU must be disabled, or the active ID map will end up
+        * getting interpreted with the wrong byte order.
         */
-1:     eor     x19, x19, #SCTLR_ELx_EE
+1:     bic     x19, x19, #SCTLR_ELx_EE
        bic     x19, x19, #SCTLR_ELx_M
        b.ne    2f
        pre_disable_mmu_workaround