[PATCH 4/4] arm64: dts: rockchip: add csi dphy nodes to rk3576
From: Amin Gattout
Date: Thu Aug 20 2026 - 10:01:54 EST
The Rockchip RK3576 features two MIPI CSI-2 DPHYs. Add the device
tree nodes for them.
Signed-off-by: Amin Gattout <amin.gattout@xxxxxxxxx>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 34 ++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index b0c0d3c8b1b1..b7a527614243 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -973,11 +973,21 @@ sdgmac_grf: syscon@26038000 {
reg = <0x0 0x26038000 0x0 0x1000>;
};
+ csidphy0_grf: syscon@2603a000 {
+ compatible = "rockchip,rk3576-csidphy-grf", "syscon";
+ reg = <0x0 0x2603a000 0x0 0x2000>;
+ };
+
ioc_grf: syscon@26040000 {
compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd";
reg = <0x0 0x26040000 0x0 0xc000>;
};
+ csidphy1_grf: syscon@2604c000 {
+ compatible = "rockchip,rk3576-csidphy-grf", "syscon";
+ reg = <0x0 0x2604c000 0x0 0x2000>;
+ };
+
cru: clock-controller@27200000 {
compatible = "rockchip,rk3576-cru";
reg = <0x0 0x27200000 0x0 0x50000>;
@@ -2848,6 +2858,30 @@ hdptxphy: hdmiphy@2b000000 {
status = "disabled";
};
+ csi_dphy0: phy@2b030000 {
+ compatible = "rockchip,rk3576-csi-dphy";
+ reg = <0x0 0x2b030000 0x0 0x10000>;
+ clocks = <&cru PCLK_CSIDPHY>;
+ clock-names = "pclk";
+ #phy-cells = <0>;
+ resets = <&cru SRST_P_CSIPHY>;
+ reset-names = "apb";
+ rockchip,grf = <&csidphy0_grf>;
+ status = "disabled";
+ };
+
+ csi_dphy1: phy@2b070000 {
+ compatible = "rockchip,rk3576-csi-dphy";
+ reg = <0x0 0x2b070000 0x0 0x10000>;
+ clocks = <&cru PCLK_CSIDPHY1>;
+ clock-names = "pclk";
+ #phy-cells = <0>;
+ resets = <&cru SRST_P_CSIDPHY1>;
+ reset-names = "apb";
+ rockchip,grf = <&csidphy1_grf>;
+ status = "disabled";
+ };
+
sram: sram@3ff88000 {
compatible = "mmio-sram";
reg = <0x0 0x3ff88000 0x0 0x78000>;
--
2.43.0