[PATCH v4 08/14] iio: adc: ad7768: Add per-channel conversion delay
From: Janani Sunil
Date: Fri Aug 21 2026 - 10:13:21 EST
Expose the per-channel synchronization phase offset through the IIO
conversion-delay attribute.
Derive the delay resolution from MCLK, power mode and decimation rate.
Validate the requested delay and program the corresponding phase
register when applying the active channel configuration.
Signed-off-by: Janani Sunil <janani.sunil@xxxxxxxxxx>
---
drivers/iio/adc/ad7768.c | 143 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 143 insertions(+)
diff --git a/drivers/iio/adc/ad7768.c b/drivers/iio/adc/ad7768.c
index 289f3fa3142e..12370139d03f 100644
--- a/drivers/iio/adc/ad7768.c
+++ b/drivers/iio/adc/ad7768.c
@@ -24,6 +24,7 @@
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/spi/spi.h>
+#include <linux/time64.h>
#include <linux/types.h>
#include <linux/unaligned.h>
#include <linux/units.h>
@@ -158,6 +159,12 @@ struct ad7768_freq_config {
unsigned int dec_rate;
};
+struct ad7768_convdelay_params {
+ unsigned int shift;
+ unsigned int max_raw;
+ u64 step_ps;
+};
+
struct ad7768_avail_freq {
unsigned int n_freqs;
unsigned int freqs[MAX_FREQ_PER_MODE];
@@ -187,6 +194,7 @@ struct ad7768_state {
unsigned int n_freqs;
int freqs[AD7768_MAX_FREQS];
unsigned int ch_freq[AD7768_MAX_CHANNEL];
+ u64 ch_convdelay_ps[AD7768_MAX_CHANNEL];
enum ad7768_filter_type ch_filter[AD7768_MAX_CHANNEL];
struct iio_backend *back;
@@ -250,6 +258,12 @@ static unsigned int ad7768_gain_reg(const struct ad7768_state *st,
return AD7768_REG_GAIN(st->chip_info->chan_map[ch]);
}
+static unsigned int ad7768_phase_reg(const struct ad7768_state *st,
+ unsigned int ch)
+{
+ return AD7768_REG_PHASE(st->chip_info->chan_map[ch]);
+}
+
static u8 ad7768_precharge_buf1_mask(const struct ad7768_state *st, u16 val)
{
return val & GENMASK(st->chip_info->prebuf_split - 1, 0);
@@ -615,6 +629,105 @@ static int ad7768_set_sampling_freq(struct iio_dev *indio_dev,
return 0;
}
+static int ad7768_get_freq_cfg(struct ad7768_state *st, unsigned int freq,
+ struct ad7768_freq_config *f_cfg)
+{
+ for (unsigned int i = 0;
+ i < st->avail_freq[st->power_mode_idx].n_freqs; i++) {
+ *f_cfg = st->avail_freq[st->power_mode_idx].freq_cfg[i];
+ if (freq == f_cfg->freq_hz)
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int ad7768_get_convdelay_params(struct ad7768_state *st, unsigned int ch,
+ struct ad7768_convdelay_params *params)
+{
+ struct ad7768_freq_config f_cfg;
+ unsigned int dec_rate;
+ unsigned int mclk_div;
+ unsigned int mult;
+ u64 mclk;
+ int ret;
+
+ ret = ad7768_get_freq_cfg(st, st->ch_freq[ch], &f_cfg);
+ if (ret)
+ return ret;
+
+ dec_rate = ad7768_dec_rate[f_cfg.dec_rate];
+ switch (dec_rate) {
+ case 32:
+ params->shift = 3;
+ params->max_raw = 31;
+ mult = 1;
+ break;
+ case 64:
+ params->shift = 2;
+ params->max_raw = 63;
+ mult = 1;
+ break;
+ case 128:
+ params->shift = 1;
+ params->max_raw = 127;
+ mult = 1;
+ break;
+ case 256:
+ params->shift = 0;
+ params->max_raw = 255;
+ mult = 1;
+ break;
+ case 512:
+ params->shift = 0;
+ params->max_raw = 255;
+ mult = 2;
+ break;
+ case 1024:
+ params->shift = 0;
+ params->max_raw = 255;
+ mult = 4;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ mclk = clk_get_rate(st->mclk);
+ if (!mclk)
+ return -EINVAL;
+
+ mclk_div = ad7768_power_modes[st->power_mode_idx].mclk_div;
+ params->step_ps = DIV_ROUND_CLOSEST_ULL((u64)mult * PSEC_PER_SEC *
+ mclk_div, mclk);
+
+ return 0;
+}
+
+static int ad7768_set_channel_convdelay(struct ad7768_state *st,
+ unsigned int ch)
+{
+ u64 delay_ps = st->ch_convdelay_ps[ch];
+ struct ad7768_convdelay_params params;
+ u64 max_delay_ps;
+ u64 raw;
+ int ret;
+
+ ret = ad7768_get_convdelay_params(st, ch, ¶ms);
+ if (ret)
+ return ret;
+
+ max_delay_ps = (u64)params.max_raw * params.step_ps;
+ if (delay_ps > max_delay_ps)
+ return -EINVAL;
+
+ raw = DIV_ROUND_CLOSEST_ULL(delay_ps, params.step_ps);
+ if (raw > params.max_raw)
+ return -EINVAL;
+
+ return regmap_write(st->regmap, ad7768_phase_reg(st, ch),
+ raw << params.shift);
+}
+
static void ad7768_filter_wait(const unsigned int *mode_freq,
const enum ad7768_filter_type *mode_filter,
const bool *mode_used)
@@ -738,6 +851,16 @@ static int ad7768_apply_channel_modes(struct iio_dev *indio_dev,
max_freq = max(max_freq, mode_freq[mode]);
}
+ for_each_set_bit(c, scan_mask, st->chip_info->num_channels) {
+ ret = ad7768_set_channel_convdelay(st, c);
+ if (ret == -EINVAL)
+ return dev_err_probe(regmap_get_device(st->regmap), ret,
+ "Invalid conversion delay for channel %u\n",
+ c);
+ if (ret)
+ return ret;
+ }
+
ret = ad7768_set_clk_divs(st, max_freq);
if (ret)
return ret;
@@ -788,6 +911,13 @@ static int ad7768_read_raw(struct iio_dev *indio_dev,
*val = calib;
return IIO_VAL_INT;
+ case IIO_CHAN_INFO_CONVDELAY: {
+ guard(mutex)(&st->lock);
+ iio_val_s64_decompose(st->ch_convdelay_ps[chan->channel],
+ val, val2);
+
+ return IIO_VAL_DECIMAL64_PICO;
+ }
default:
return -EINVAL;
}
@@ -801,6 +931,8 @@ static int ad7768_write_raw_get_fmt(struct iio_dev *indio_dev,
case IIO_CHAN_INFO_CALIBBIAS:
case IIO_CHAN_INFO_CALIBSCALE:
return IIO_VAL_INT;
+ case IIO_CHAN_INFO_CONVDELAY:
+ return IIO_VAL_DECIMAL64_PICO;
default:
return -EINVAL;
}
@@ -812,6 +944,7 @@ static int ad7768_write_raw(struct iio_dev *indio_dev,
{
struct ad7768_state *st = iio_priv(indio_dev);
unsigned int base_reg;
+ s64 delay_ps;
int ret;
IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
@@ -838,6 +971,15 @@ static int ad7768_write_raw(struct iio_dev *indio_dev,
base_reg = ad7768_get_calib_reg_base(st, chan, true);
return ad7768_write_calib_value(st, base_reg, val);
+ case IIO_CHAN_INFO_CONVDELAY: {
+ delay_ps = iio_val_s64_compose(val, val2);
+ if (delay_ps < 0)
+ return -EINVAL;
+
+ guard(mutex)(&st->lock);
+ st->ch_convdelay_ps[chan->channel] = delay_ps;
+ return 0;
+ }
default:
return -EINVAL;
}
@@ -1133,6 +1275,7 @@ static int ad7768_parse_config(struct iio_dev *indio_dev,
.type = IIO_VOLTAGE,
.info_mask_separate = BIT(IIO_CHAN_INFO_CALIBBIAS) |
BIT(IIO_CHAN_INFO_CALIBSCALE) |
+ BIT(IIO_CHAN_INFO_CONVDELAY) |
BIT(IIO_CHAN_INFO_SAMP_FREQ),
.info_mask_separate_available =
BIT(IIO_CHAN_INFO_SAMP_FREQ),
--
2.43.0