[PATCH 08/16] arm64: dts: st: Add ucpd node on stm32mp251

From: Fabrice Gasnier

Date: Fri Aug 21 2026 - 12:24:54 EST


Describe UCPD bindings and nvmem cells to access trim values.
This provides the PD and CC USB-C cable signaling functions.

Co-developed-by: Christian Bruel <christian.bruel@xxxxxxxxxxx>
Signed-off-by: Christian Bruel <christian.bruel@xxxxxxxxxxx>
Co-developed-by: Thomas Bourgoin <thomas.bourgoin@xxxxxxxxxxx>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@xxxxxxxxxxx>
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@xxxxxxxxxxx>
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 51 ++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)

diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 9dc7a05fce99..be54dd56713b 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -1637,6 +1637,27 @@ dcmipp: dcmipp@48030000 {
status = "disabled";
};

+ ucpd: typec@480a0000 {
+ compatible = "st,stm32mp25-ucpd";
+ reg = <0x480a0000 0x400>;
+ interrupts-extended = <&exti1 46 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ucpd";
+ clocks = <&rcc CK_BUS_USBTC>, <&rcc CK_KER_USBTC>;
+ clock-names = "apb", "ker";
+ resets = <&rcc USBTC_R>;
+ reset-names = "ucpd";
+ nvmem-cells = <&ucpd_trim_rd_cc1 &ucpd_trim_rd_cc2
+ &ucpd_trim_3a_cc1 &ucpd_trim_3a_cc2
+ &ucpd_trim_1a5_cc1 &ucpd_trim_1a5_cc2>;
+ nvmem-cell-names = "trim_rd_cc1", "trim_rd_cc2",
+ "trim_3a_cc1", "trim_3a_cc2",
+ "trim_1a5_cc1", "trim_1a5_cc2";
+ ucpd-supply = <&scmi_vdd33ucpd>;
+ access-controllers = <&rifsc 69>;
+ power-domains = <&CLUSTER_PD>;
+ status = "disabled";
+ };
+
combophy: phy@480c0000 {
compatible = "st,stm32mp25-combophy";
reg = <0x480c0000 0x1000>;
@@ -1818,10 +1839,40 @@ part-number-otp@24 {
reg = <0x24 0x4>;
};

+ ucpd_trim_3a_cc1: trim_3a_cc1@1bd,1 {
+ reg = <0x1bd 0x1>;
+ bits = <1 4>;
+ };
+
+ ucpd_trim_3a_cc2: trim_3a_cc2@1bf,1 {
+ reg = <0x1bf 0x1>;
+ bits = <1 4>;
+ };
+
package-otp@1e8 {
reg = <0x1e8 0x1>;
bits = <0 3>;
};
+
+ ucpd_trim_rd_cc1: trim_rd_cc1@1e8,4 {
+ reg = <0x1e8 0x1>;
+ bits = <4 4>;
+ };
+
+ ucpd_trim_1a5_cc1: trim_1a5_cc1@1e9,0 {
+ reg = <0x1e9 0x1>;
+ bits = <0 4>;
+ };
+
+ ucpd_trim_rd_cc2: trim_rd_cc2@1e9,4 {
+ reg = <0x1e9 0x1>;
+ bits = <4 4>;
+ };
+
+ ucpd_trim_1a5_cc2: trim_1a5_cc2@1ea,0 {
+ reg = <0x1ea 0x1>;
+ bits = <0 4>;
+ };
};

hdp: pinctrl@44090000 {

--
2.43.0