Re: [PATCH v2 05/10] drm/nouveau/disp: fix HDMI GCP AVMute register offsets on GB20x

[lyude]

Code-wise this looks totally fine, but I'm not actually getting any
audio on my local GB206 setup. Is this expected, e.g. will we need more
work to actually get it working?

On Thu, 2026-08-20 at 20:49 +0400, Mohamed Ahmed wrote:
> The GSP path brackets audio enablement with a General Control Packet
> AVMute toggle. r535_sor_hdmi_audio() calls the gsp.hdmi_gcp hook,
> which
> every chip so far serves with tu102_sor_hdmi_gcp() and the legacy GCP
> unit at 0x6f00c0/0x6f00cc. On GB20x the SF packet units were
> compacted
> and the old generic and VSI units are gone (ACR keeps slot 2) and the
> GCP unit moved from slot 3 to slot 1 (control 0x6f0040 and subpack
> 0x6f004c from NVIDIA's published clc971.h. The same offsets are also
> used by OpenRM's hdmiWriteGeneralCtrlPacketC871() on these chips).
> The
> old addresses are reserved on GB20x, so the AVMute writes were silent
> no-ops and mitigated only by the equivalent GCP r535_sor_hdmi_audio()
> already sends through the SET_OD_PACKET RM control.
> 
> Add a GB20x GCP writer using the new offsets and hook it into
> gb202_gsp_disp, keeping the direct MMIO path in sync with the
> hardware
> as on earlier chips.
> 
> Only SB0 (the AVMute bit) is written. On NVD5.0 the subpack register
> also
> carries SB1_CTRL (bit 24), which selects where the deep-color CD/PP
> fields are generated (hardware or from the driver, with the default
> being
> HW). hdmiWriteGeneralCtrlPacketC871() likewise writes only SB0-SB2.
> 
> Signed-off-by: Mohamed Ahmed <mohamedahmedegypt2001@xxxxxxxxx>
> ---
>  .../gpu/drm/nouveau/nvkm/engine/disp/gb202.c  | 20
> ++++++++++++++++++-
>  1 file changed, 19 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c
> b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c
> index fa83aee35ae7..4863b2b36db0 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c
> @@ -65,6 +65,24 @@ gb202_sor_hdmi_infoframe_vsi(struct nvkm_ior *ior,
> int head, void *data, u32 siz
>  	nvkm_wr32(device, 0x6f03f8 + hoff, 0x00000002);
>  }
>  
> +/* General Control Packet AVMute bracket. The GCP unit moved to slot
> 1 on
> + * NVD5.0. Only SB0 (the AVMute bit) is ours to write so we must not
> do a
> + * full write here: SB1 carries the deep-color CD/PP fields, and
> SB1_CTRL
> + * (bit 24, new with clc871.h) controls where their generation
> happens (HW
> + * or driver) on these chips, with the default being HW.
> + */
> +static void
> +gb202_sor_hdmi_gcp(struct nvkm_ior *sor, int head, bool enable)
> +{
> +	struct nvkm_device *device = sor->disp-
> >engine.subdev.device;
> +	const u32 hdmi = head * 0x400;
> +
> +	nvkm_mask(device, 0x6f0040 + hdmi, 0x00000001, 0x00000000);
> +	nvkm_mask(device, 0x6f004c + hdmi, 0x000000ff, !enable ?
> 0x00000001 :
> +								
> 0x00000010);
> +	nvkm_mask(device, 0x6f0040 + hdmi, 0x00000001, 0x00000001);
> +}
> +
>  /* GB20x is GSP-only. This table supplies the register programming
> the
>   * GSP-RM display path needs from the chip.
>   */
> @@ -77,7 +95,7 @@ gb202_gsp_disp = {
>  	.gsp.head_rgpos = gv100_head_rgpos,
>  	.gsp.vblank_get = tu102_head_vblank_get,
>  	.gsp.vblank_put = tu102_head_vblank_put,
> -	.gsp.hdmi_gcp = tu102_sor_hdmi_gcp,
> +	.gsp.hdmi_gcp = gb202_sor_hdmi_gcp,
>  	/* The legacy AVI unit is unchanged on GB20x. */
>  	.gsp.hdmi_infoframe_avi = gv100_sor_hdmi_infoframe_avi,
>  	.gsp.hdmi_infoframe_vsi = gb202_sor_hdmi_infoframe_vsi,