[PATCH 11/12] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree

From: Jia Wang via B4 Relay

Date: Mon Aug 24 2026 - 02:18:08 EST

From: Jia Wang <wangjia@xxxxxxxxxxxxx>

Shenzhen Rongda M0 is an mATX motherboard based on the UltraRISC DP1000
SoC.

Signed-off-by: Jia Wang <wangjia@xxxxxxxxxxxxx>
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/ultrarisc/Makefile | 2 +
arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h | 63 ++++++++++++
.../ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi | 79 ++++++++++++++
.../boot/dts/ultrarisc/dp1000-shenrongda-m0.dts | 114 +++++++++++++++++++++
5 files changed, 259 insertions(+)

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 69d8751fb17c..702882974251 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -12,3 +12,4 @@ subdir-y += spacemit
subdir-y += starfive
subdir-y += tenstorrent
subdir-y += thead
+subdir-y += ultrarisc
diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile
new file mode 100644
index 000000000000..454d849a6ce4
--- /dev/null
+++ b/arch/riscv/boot/dts/ultrarisc/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-shenrongda-m0.dtb
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h
new file mode 100644
index 000000000000..4668e45d2335
--- /dev/null
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-pinctrl.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+#ifndef _DP1000_PINCTRL_H
+#define _DP1000_PINCTRL_H
+
+#define PA0 0
+#define PA1 1
+#define PA2 2
+#define PA3 3
+#define PA4 4
+#define PA5 5
+#define PA6 6
+#define PA7 7
+#define PA8 8
+#define PA9 9
+#define PA10 10
+#define PA11 11
+#define PA12 12
+#define PA13 13
+#define PA14 14
+#define PA15 15
+#define PB0 16
+#define PB1 17
+#define PB2 18
+#define PB3 19
+#define PB4 20
+#define PB5 21
+#define PB6 22
+#define PB7 23
+#define PC0 24
+#define PC1 25
+#define PC2 26
+#define PC3 27
+#define PC4 28
+#define PC5 29
+#define PC6 30
+#define PC7 31
+#define PD0 32
+#define PD1 33
+#define PD2 34
+#define PD3 35
+#define PD4 36
+#define PD5 37
+#define PD6 38
+#define PD7 39
+#define LPC0 40
+#define LPC1 41
+#define LPC2 42
+#define LPC3 43
+#define LPC4 44
+#define LPC5 45
+#define LPC6 46
+#define LPC7 47
+#define LPC8 48
+#define LPC9 49
+#define LPC10 50
+#define LPC11 51
+#define LPC12 52
+
+#endif /* _DP1000_PINCTRL_H */
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi
new file mode 100644
index 000000000000..ab927c6cd614
--- /dev/null
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0-pinctrl.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+#include "dp1000.dtsi"
+#include "dp1000-pinctrl.h"
+
+&pinctrl {
+ i2c0_pins: i2c0-pins {
+ pins = <PA12 PA13>;
+ function = "i2c";
+ bias-pull-up;
+ drive-strength = <33>;
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins = <PB6 PB7>;
+ function = "i2c";
+ bias-pull-up;
+ drive-strength = <33>;
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins = <PC0 PC1>;
+ function = "i2c";
+ bias-pull-up;
+ drive-strength = <33>;
+ };
+
+ i2c3_pins: i2c3-pins {
+ pins = <PC2 PC3>;
+ function = "i2c";
+ bias-pull-up;
+ drive-strength = <33>;
+ };
+
+ spi0_pins: spi0-pins {
+ pins = <PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7>;
+ function = "spi";
+ bias-pull-up;
+ drive-strength = <33>;
+ };
+
+ spi1_pins: spi1-pins {
+ pins = <PA0 PA1 PA2 PA3>;
+ function = "spi";
+ bias-pull-up;
+ drive-strength = <33>;
+ };
+
+ uart0_pins: uart0-pins {
+ pins = <PA8 PA9>;
+ function = "uart";
+ bias-pull-up;
+ drive-strength = <33>;
+ };
+
+ uart1_pins: uart1-pins {
+ pins = <PB4 PB5>;
+ function = "uart";
+ bias-pull-up;
+ drive-strength = <33>;
+ };
+
+ uart2_pins: uart2-pins {
+ pins = <PC4 PC5>;
+ function = "uart";
+ bias-pull-up;
+ drive-strength = <33>;
+ };
+
+ uart3_pins: uart3-pins {
+ pins = <PC6 PC7>;
+ function = "uart";
+ bias-pull-up;
+ drive-strength = <33>;
+ };
+};
diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts
new file mode 100644
index 000000000000..da831da819ef
--- /dev/null
+++ b/arch/riscv/boot/dts/ultrarisc/dp1000-shenrongda-m0.dts
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
+ */
+
+#include "dp1000-shenrongda-m0-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Shenzhen Rongda M0 Board";
+ compatible = "shenrongda,m0", "ultrarisc,dp1000";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ rtc@32 {
+ compatible = "whwave,sd3078";
+ reg = <0x32>;
+ };
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+};
+
+&spi1 {
+ num-cs = <1>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+};
+
+&pcie_x16 {
+ status = "okay";
+};
+
+&pcie_x4a {
+ status = "okay";
+};
+
+&pcie_x4b {
+ status = "okay";
+};
+
+&ethernet {
+ phy-handle = <&phy0>;
+ /*
+ * YT8531 RGMII timing on this board requires no PHY internal delays.
+ * Using "rgmii-id" together with rx/tx-internal-delay-ps results in RX CRC
+ * errors and no usable traffic, so keep plain "rgmii" here.
+ */
+ phy-mode = "rgmii";
+
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: phy@0 {
+ reg = <0>;
+ };
+ };
+};

--
2.34.1