Re: [PATCH v4 2/8] clk: starfive: Add system-0 domain PLL clock driver

[Changhuang Liang]

Hi, Brian

> > On Sat, Aug 08, 2026 at 06:50:48PM -0700, Changhuang Liang wrote:
> > > Add system-0 domain PLL clock driver for StarFive JHB100 SoC.
> > >
> > > Signed-off-by: Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
> > > ---
> > >  drivers/clk/starfive/Kconfig                  |   8 +
> > >  drivers/clk/starfive/Makefile                 |   1 +
> > >  .../clk/starfive/clk-starfive-jhb100-pll.c    | 535
> ++++++++++++++++++
> > >  3 files changed, 544 insertions(+)
> > >  create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-pll.c
> > >
> > > diff --git a/drivers/clk/starfive/Kconfig
> > > b/drivers/clk/starfive/Kconfig index 852464949334..a39dd22112fa
> > > 100644
> > > --- a/drivers/clk/starfive/Kconfig
> > > +++ b/drivers/clk/starfive/Kconfig
> > > @@ -117,6 +117,14 @@ config CLK_STARFIVE_JHB100_PER3
> > >  	  Say yes here to support the peripheral-3 clock controller
> > >  	  on the StarFive JHB100 SoC.
> > >
> > > +config CLK_STARFIVE_JHB100_PLL
> > > +	bool "StarFive JHB100 PLL clock support"
> >
> > Can this be a tristate?
> 
> I checked again, this doesn't affect the critical clock, so it can be changed to
> tristate

I need to correct this again, this affects the clock registration during startup, 
so it cannot be changed to tristate.

Best Regards,
Changhuang