[PATCH v4 7/8] iio: adc: ti-ads1015: replace custom shift macros with FIELD_PREP/GET
From: Archit Anant
Date: Thu Aug 27 2026 - 13:25:05 EST
The driver currently uses custom _SHIFT macros and manual bitwise
operations to read and write to the configuration register.
Modernize the bitwise logic by replacing all manual shifts with the
standard FIELD_PREP() and FIELD_GET() macros from <linux/bitfield.h>.
This improves readability and prevents potential bitwise errors.
Remove the now-unused _SHIFT macros from the top of the file.
Suggested-by: Jonathan Cameron <jic23@xxxxxxxxxx>
Signed-off-by: Archit Anant <architanant5@xxxxxxxxx>
---
drivers/iio/adc/ti-ads1015.c | 40 +++++++++++++++---------------------
1 file changed, 16 insertions(+), 24 deletions(-)
diff --git a/drivers/iio/adc/ti-ads1015.c b/drivers/iio/adc/ti-ads1015.c
index a6dd85debc0e..d675f82c0bd5 100644
--- a/drivers/iio/adc/ti-ads1015.c
+++ b/drivers/iio/adc/ti-ads1015.c
@@ -11,6 +11,7 @@
* * 0x4B - ADDR connected to SCL
*/
+#include <linux/bitfield.h>
#include <linux/cleanup.h>
#include <linux/delay.h>
#include <linux/i2c.h>
@@ -39,14 +40,7 @@
#define ADS1015_LO_THRESH_REG 0x02
#define ADS1015_HI_THRESH_REG 0x03
-#define ADS1015_CFG_COMP_QUE_SHIFT 0
-#define ADS1015_CFG_COMP_LAT_SHIFT 2
-#define ADS1015_CFG_COMP_POL_SHIFT 3
-#define ADS1015_CFG_COMP_MODE_SHIFT 4
-#define ADS1015_CFG_DR_SHIFT 5
#define ADS1015_CFG_MOD_SHIFT 8
-#define ADS1015_CFG_PGA_SHIFT 9
-#define ADS1015_CFG_MUX_SHIFT 12
#define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0)
#define ADS1015_CFG_COMP_LAT_MASK BIT(2)
@@ -408,15 +402,15 @@ int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
dr = data->channel_data[chan].data_rate;
mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
ADS1015_CFG_DR_MASK;
- cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
- dr << ADS1015_CFG_DR_SHIFT;
+ cfg = FIELD_PREP(ADS1015_CFG_MUX_MASK, chan) | FIELD_PREP(ADS1015_CFG_PGA_MASK, pga) |
+ FIELD_PREP(ADS1015_CFG_DR_MASK, dr);
if (ads1015_event_channel_enabled(data)) {
mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK;
- cfg |= data->thresh_data[chan].comp_queue <<
- ADS1015_CFG_COMP_QUE_SHIFT |
- data->comp_mode <<
- ADS1015_CFG_COMP_MODE_SHIFT;
+ cfg |= FIELD_PREP(ADS1015_CFG_COMP_QUE_MASK,
+ data->thresh_data[chan].comp_queue) |
+ FIELD_PREP(ADS1015_CFG_COMP_MODE_MASK,
+ data->comp_mode);
}
cfg = (old & ~mask) | (cfg & mask);
@@ -427,7 +421,7 @@ int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
data->conv_invalid = true;
}
if (data->conv_invalid) {
- dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT;
+ dr_old = FIELD_GET(ADS1015_CFG_DR_MASK, old);
conv_time = DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr_old]);
conv_time += DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr]);
conv_time += conv_time / 10; /* 10% internal clock inaccuracy */
@@ -744,6 +738,7 @@ static int ads1015_enable_event_config(struct ads1015_data *data,
static int ads1015_disable_event_config(struct ads1015_data *data,
const struct iio_chan_spec *chan, int comp_mode)
{
+ unsigned int val = FIELD_PREP(ADS1015_CFG_COMP_QUE_MASK, ADS1015_CFG_COMP_DISABLE);
int ret;
if (!ads1015_event_channel_enabled(data))
@@ -756,10 +751,7 @@ static int ads1015_disable_event_config(struct ads1015_data *data,
comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)
return 0;
- ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
- ADS1015_CFG_COMP_QUE_MASK,
- ADS1015_CFG_COMP_DISABLE <<
- ADS1015_CFG_COMP_QUE_SHIFT);
+ ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG, ADS1015_CFG_COMP_QUE_MASK, val);
if (ret)
return ret;
@@ -1005,19 +997,19 @@ static int ads1015_probe(struct i2c_client *client)
unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK |
ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK;
unsigned int cfg_comp =
- ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT |
- 1 << ADS1015_CFG_COMP_LAT_SHIFT;
+ FIELD_PREP(ADS1015_CFG_COMP_QUE_MASK, ADS1015_CFG_COMP_DISABLE) |
+ FIELD_PREP(ADS1015_CFG_COMP_LAT_MASK, 1);
switch (irq_trig) {
case IRQF_TRIGGER_FALLING:
case IRQF_TRIGGER_LOW:
- cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
- ADS1015_CFG_COMP_POL_SHIFT;
+ cfg_comp |= FIELD_PREP(ADS1015_CFG_COMP_POL_MASK,
+ ADS1015_CFG_COMP_POL_LOW);
break;
case IRQF_TRIGGER_HIGH:
case IRQF_TRIGGER_RISING:
- cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
- ADS1015_CFG_COMP_POL_SHIFT;
+ cfg_comp |= FIELD_PREP(ADS1015_CFG_COMP_POL_MASK,
+ ADS1015_CFG_COMP_POL_HIGH);
break;
default:
return -EINVAL;
--
2.39.5