Re: [PATCH] ata: pata_pdc2027x: fix division by zero in pdc_adjust_pll

[Damien Le Moal]

On 8/25/26 17:32, Yang Zi wrote:
> pdc_adjust_pll() divides pout_required by pll_clock_khz before checking
> that pll_clock_khz is within the valid range. If the PLL input clock is
> less than 1000 Hz, pll_clock_khz is 0 and the division triggers a
> divide-by-zero error.
> 
> Move the sanity check ahead of the division so the invalid input is
> rejected before the ratio is computed.
> 
> Signed-off-by: Yang Zi <2959243019@xxxxxx>

This is needs a fixes tag I think.

Other than that, looks OK.

Reviewed-by: Damien Le Moal <dlemoal@xxxxxxxxxx>

-- 
Damien Le Moal
Western Digital Research