[PATCH v6 13/21] dt-bindings: pinctrl: Add starfive,jhb100-per1-pinctrl
From: Changhuang Liang
Date: Fri Aug 28 2026 - 23:15:08 EST
Add pinctrl bindings for StarFive JHB100 SoC Peripheral-1(per1) pinctrl
controller.
On the StarFive JHB100 SoC, every 32 GPIOs correspond to one register
address. Therefore, under this model, every 32 GPIOs can be regarded
as one GPIO instance. In this case, the following new approach can be
used to represent this model:
gpios = <&gpio [instance] offset flags>;
gpio-ranges = <&pinctrl [gpio_instance] gpio_offset pin_offset count>;
At the same time, this model also reduces the /32 and %32 operations
in the driver.
Signed-off-by: Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
---
.../pinctrl/starfive,jhb100-per1-pinctrl.yaml | 179 ++++++++++++++++++
.../pinctrl/starfive,jhb100-pinctrl.h | 38 ++++
2 files changed, 217 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml
new file mode 100644
index 000000000000..85b64e2bbd53
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per1-pinctrl.yaml
@@ -0,0 +1,179 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 Peripheral-1 Pin Controller
+
+description: |
+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.
+
+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
+ per2, per2pok, per3, adc0, adc1, emmc, and vga.
+ This document provides an overview of the "per1" pinctrl domain.
+
+ The "per1" domain has a pin controller which provides
+ - function selection for GPIO pads.
+ - GPIO pad configuration.
+ - GPIO interrupt handling.
+
+ In the Peripheral-1 Pin Controller, there are 36 multi-function GPIO_PADs.
+ Each of them can be multiplexed to several peripherals through function
+ selection. Each iopad has a maximum of up to 3 functions - 0, 1, and 2.
+ Function 0 is the default function which is generally the GPIO function.
+ Function 1 and 2 are the alternate functions or peripheral signals that
+ can be routed to the iopad. The function selection can be carried out by
+ writing the function number to the iopad function select register.
+
+ Each iopad is configurable with parameters such as input-enable, internal
+ pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input
+ debounce nanoseconds, power source and drive type (open-drain or push-pull).
+
+maintainers:
+ - Changhuang Liang <changhuang.liang@xxxxxxxxxxxxxxxx>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jhb100-per1-pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 3
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 3
+
+ gpio-ranges: true
+
+ gpio-line-names: true
+
+patternProperties:
+ '-grp$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '-pins$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnode representing the
+ pinctrl groups available in the domain. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to
+ function selection, bias, input enable/disable, input schmitt
+ trigger enable/disable, slew-rate, input debounce nanoseconds,
+ drive-open-drain, drive-push-pull, power-source and drive-strength.
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+ properties:
+ pins:
+ description:
+ The list of IOs that properties in the pincfg node apply to.
+
+ function:
+ description:
+ A string containing the name of the function to mux for these
+ pins.
+ enum: [ gpio, i2c, sfc, sgpio, spi ]
+
+ bias-disable: true
+
+ bias-pull-down:
+ type: boolean
+
+ bias-pull-up:
+ oneOf:
+ - type: boolean
+ - enum: [ 600, 900, 1200, 2000 ]
+ description: Pull up RSEL type resistance values (in ohms)
+ description:
+ For normal pull up type there is no need to specify a resistance
+ value, hence this can be specified as a boolean property.
+ For RSEL pull up type a resistance value (in ohms) can be added.
+
+ drive-open-drain: true
+
+ drive-push-pull: true
+
+ drive-strength:
+ enum: [ 2, 4, 8, 12 ]
+
+ drive-strength-microamp:
+ enum: [ 2000, 4000, 8000, 12000 ]
+
+ input-debounce-ns:
+ minimum: 0
+ maximum: 10485680
+ description:
+ Debounce time in nanoseconds. The hardware counts in 80 ns
+ stages with a 17-bit counter, so the maximum is 10485680 ns.
+
+ input-disable: true
+
+ input-enable: true
+
+ input-schmitt-enable: true
+
+ input-schmitt-disable: true
+
+ power-source:
+ enum: [ 1800, 3300 ]
+ description: I/O voltage in millivolt.
+
+ slew-rate:
+ enum: [ 0, 1 ]
+ default: 0
+ description: |
+ 0: slow
+ 1: fast
+
+required:
+ - compatible
+ - reg
+ - resets
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl_per1: pinctrl@11b42000 {
+ compatible = "starfive,jhb100-per1-pinctrl";
+ reg = <0x0 0x11b42000 0x0 0x800>;
+ resets = <&per1crg 0>;
+ interrupts = <61>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ gpio-ranges = <&pinctrl_per1 0 0 0 32>,
+ <&pinctrl_per1 1 0 32 4>;
+ };
+ };
diff --git a/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h b/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h
index e0ad453d6884..9f622468c294 100644
--- a/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h
+++ b/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h
@@ -139,4 +139,42 @@
#define PADNUM_PER0_GPIO_B58 58
#define PADNUM_PER0_GPIO_B59 59
+/* per1 pad numbers */
+#define PADNUM_PER1_GPIO_C0 0
+#define PADNUM_PER1_GPIO_C1 1
+#define PADNUM_PER1_GPIO_C2 2
+#define PADNUM_PER1_GPIO_C3 3
+#define PADNUM_PER1_GPIO_C4 4
+#define PADNUM_PER1_GPIO_C5 5
+#define PADNUM_PER1_GPIO_C6 6
+#define PADNUM_PER1_GPIO_C7 7
+#define PADNUM_PER1_GPIO_C8 8
+#define PADNUM_PER1_GPIO_C9 9
+#define PADNUM_PER1_GPIO_C10 10
+#define PADNUM_PER1_GPIO_C11 11
+#define PADNUM_PER1_GPIO_C12 12
+#define PADNUM_PER1_GPIO_C13 13
+#define PADNUM_PER1_GPIO_C14 14
+#define PADNUM_PER1_GPIO_C15 15
+#define PADNUM_PER1_GPIO_C16 16
+#define PADNUM_PER1_GPIO_C17 17
+#define PADNUM_PER1_GPIO_C18 18
+#define PADNUM_PER1_GPIO_C19 19
+#define PADNUM_PER1_GPIO_C20 20
+#define PADNUM_PER1_GPIO_C21 21
+#define PADNUM_PER1_GPIO_C22 22
+#define PADNUM_PER1_GPIO_C23 23
+#define PADNUM_PER1_GPIO_C24 24
+#define PADNUM_PER1_GPIO_C25 25
+#define PADNUM_PER1_GPIO_C26 26
+#define PADNUM_PER1_GPIO_C27 27
+#define PADNUM_PER1_GPIO_C28 28
+#define PADNUM_PER1_GPIO_C29 29
+#define PADNUM_PER1_GPIO_C30 30
+#define PADNUM_PER1_GPIO_C31 31
+#define PADNUM_PER1_GPIO_C32 32
+#define PADNUM_PER1_GPIO_C33 33
+#define PADNUM_PER1_GPIO_C34 34
+#define PADNUM_PER1_GPIO_C35 35
+
#endif
--
2.25.1