[PATCH v1 4/4] arm64: dts: cix: Add USB4/USB5 nodes for Sky1

[Hongliang Yang]

Add USB4 and USB5 controller nodes (based on Cadence USBSSP DRD)
and their associated USB3 PHY nodes for the CIX Sky1 SoC. Enable
USB4 and USB5 in host mode on the Radxa Orion O6 board.

Signed-off-by: Hongliang Yang <hongliang.yang@xxxxxxxxxxx>
---
 arch/arm64/boot/dts/cix/sky1-orion-o6.dts |  36 ++++++
 arch/arm64/boot/dts/cix/sky1.dtsi         | 133 ++++++++++++++++++++++
 2 files changed, 169 insertions(+)

diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
index e39c87774c12..33d3ffdc3f9e 100644
--- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
+++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
@@ -80,6 +80,22 @@ pins {
 
 		};
 	};
+
+	pinctrl_usb4: usb4-power-on-cfg {
+		pins {
+			pinmux = <CIX_PAD_GPIO041_FUNC_USB_DRIVE_VBUS4>;
+			bias-pull-down;
+			drive-strength = <8>;
+		};
+	};
+
+	pinctrl_usb5: usb5-power-on-cfg {
+		pins {
+			pinmux = <CIX_PAD_GPIO042_FUNC_USB_DRIVE_VBUS5>;
+			bias-pull-down;
+			drive-strength = <8>;
+		};
+	};
 };
 
 &pcie_x8_rc {
@@ -117,3 +133,23 @@ &s5_gpio2 {
 &uart2 {
 	status = "okay";
 };
+
+&usb4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb4>;
+};
+
+&usbss_4 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&usb5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb5>;
+};
+
+&usbss_5 {
+	status = "okay";
+	dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index a77c52296ebd..44736c071573 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -6,6 +6,8 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/cix,sky1.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset/cix,sky1-s5-system-control.h>
 #include "sky1-power.h"
 
 / {
@@ -13,6 +15,11 @@ / {
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		usb4 = &usb4;
+		usb5 = &usb5;
+	};
+
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
@@ -574,6 +581,132 @@ mbox_ap2sfh: mailbox@80a0000 {
 			cix,mbox-dir = "tx";
 		};
 
+		usb4: usb@91c0300 {
+			compatible = "cix,sky1-usbssp";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			reg = <0x00 0x091c0314 0x00 0x4>,
+				<0x00 0x091c0400 0x00 0x4>;
+			reg-names = "axi_property", "controller_status";
+
+			resets = <&s5_syscon SKY1_USBC_SS2_PRST_N>,
+				<&s5_syscon SKY1_USBC_SS2_RST_N>;
+			reset-names = "usb_preset", "usb_reset";
+
+			clocks = <&scmi_clk CLK_TREE_USB3A_H0_CLK_SOF>,
+				<&scmi_clk CLK_TREE_USB3A_0_AXI_GATE>,
+				<&scmi_clk CLK_TREE_USB3A_H0_CLK_LPM>,
+				<&scmi_clk CLK_TREE_USB3A_0_APB_GATE>;
+			clock-names = "sof_clk", "usb_aclk", "lpm_clk", "usb_pclk";
+
+			cix,usb_syscon = <&s5_syscon>;
+			axi_bmax_value = <0x7>;
+			sof_clk_freq = <8000000>;
+			lpm_clk_freq = <32000>;
+			status = "disabled";
+
+			usbss_4: usb-controller@91d0000 {
+				compatible = "cdns,usb3";
+				reg = <0x00 0x91d0000 0x00 0x4000>,
+					<0x00 0x91d4000 0x00 0x4000>,
+					<0x00 0x91d8000 0x00 0x8000>;
+				reg-names = "otg", "dev", "xhci";
+
+				interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
+					<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
+					<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
+					<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+				interrupt-names = "host",
+					"peripheral",
+					"otg",
+					"wakeup";
+
+				maximum-speed = "super-speed-plus";
+				dr_mode = "otg";
+				phys = <&usb3_phy4_0>;
+				phy-names = "cdns3,usb3-phy";
+				status = "disabled";
+			};
+		};
+
+		usb5: usb@91c0304 {
+			compatible = "cix,sky1-usbssp";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			reg = <0x00 0x091c0324 0x00 0x4>,
+				<0x00 0x091c0410 0x00 0x4>;
+			reg-names = "axi_property", "controller_status";
+
+			resets = <&s5_syscon SKY1_USBC_SS3_PRST_N>,
+				<&s5_syscon SKY1_USBC_SS3_RST_N>;
+			reset-names = "usb_preset", "usb_reset";
+
+			clocks = <&scmi_clk CLK_TREE_USB3A_H1_CLK_SOF>,
+				<&scmi_clk CLK_TREE_USB3A_1_AXI_GATE>,
+				<&scmi_clk CLK_TREE_USB3A_H1_CLK_LPM>,
+				<&scmi_clk CLK_TREE_USB3A_1_APB_GATE>;
+			clock-names = "sof_clk", "usb_aclk", "lpm_clk", "usb_pclk";
+
+			cix,usb_syscon = <&s5_syscon>;
+			axi_bmax_value = <0x7>;
+			sof_clk_freq = <8000000>;
+			lpm_clk_freq = <32000>;
+			status = "disabled";
+
+			usbss_5: usb-controller@91e0000 {
+				compatible = "cdns,usb3";
+				reg = <0x00 0x91e0000 0x00 0x4000>,
+					<0x00 0x91e4000 0x00 0x4000>,
+					<0x00 0x91e8000 0x00 0x8000>;
+				reg-names = "otg", "dev", "xhci";
+
+				interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
+					<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
+					<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
+					<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>;
+				interrupt-names = "host",
+					"peripheral",
+					"otg",
+					"wakeup";
+
+				maximum-speed = "super-speed-plus";
+				dr_mode = "otg";
+				phys = <&usb3_phy4_1>;
+				phy-names = "cdns3,usb3-phy";
+				status = "disabled";
+			};
+		};
+
+		usb3_phy4: usb-phy@9210000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "cix,sky1-usb3-phy";
+			reg = <0x00 0x09210000 0x00 0x40000>;
+			status = "disabled";
+
+			resets = <&s5_syscon SKY1_USBPHY_SS_RST_N>,
+				<&s5_syscon SKY1_USBPHY_SS_PST_N>;
+			reset-names = "reset", "preset";
+
+			clocks = <&scmi_clk CLK_TREE_USB3A_PHY3_GATE>,
+				<&scmi_clk CLK_TREE_USB3A_PHY_x2_REF>;
+			clock-names = "apb_clk", "ref_clk";
+
+			usb3_phy4_0: usb-port@0 {
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+
+			usb3_phy4_1: usb-port@1 {
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+		};
+
 		pcie_x8_rc: pcie@a010000 {
 			compatible = "cix,sky1-pcie-host";
 			reg = <0x00 0x0a010000 0x00 0x10000>,
-- 
2.54.0