[PATCH v11 07/23] x86/resctrl: Add special case for Intel Haswell enumeration

[Tony Luck]

Certain Intel Haswell CPUs have support for resctrl L3 cache allocation
but do not enumerate the feature. There is a quirk to check for support
and provide hard-coded parameters. This quirk sets rdt_alloc_capable
to indicate to get_rdt_alloc_resources() that normal enumeration is
not needed.

Replace the set and test of rdt_alloc_capable with a new variable
in preparation for the removal of rdt_alloc_capable.

Signed-off-by: Tony Luck <tony.luck@xxxxxxxxx>
---
v11:
	New patch

 arch/x86/kernel/cpu/resctrl/core.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index b657eab4eb0c..62b97e357ce5 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -138,6 +138,9 @@ struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l)
 	return &rdt_resources_all[l].r_resctrl;
 }
 
+/* Skip regular allocation if cache_alloc_hsw_probe() succeeds. */
+static bool hsw_alloc_capable;
+
 /*
  * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs
  * as they do not have CPUID enumeration support for Cache allocation.
@@ -178,7 +181,7 @@ static inline void cache_alloc_hsw_probe(void)
 	r->cache.arch_has_sparse_bitmasks = false;
 	r->alloc_capable = true;
 
-	rdt_alloc_capable = true;
+	hsw_alloc_capable = true;
 }
 
 /*
@@ -930,7 +933,7 @@ static __init bool get_rdt_alloc_resources(void)
 	struct rdt_resource *r;
 	bool ret = false;
 
-	if (rdt_alloc_capable)
+	if (hsw_alloc_capable)
 		return true;
 
 	if (!boot_cpu_has(X86_FEATURE_RDT_A))
-- 
2.55.0