Re: (subset) [PATCH v10 0/5] Add QMP PCIe Multi-PHY support

[Bjorn Andersson]

On Tue, 25 Aug 2026 19:59:19 -0700, Qiang Yu wrote:
> Some QMP PCIe PHY hardware blocks can be configured through a link-mode
> register into different link topologies, such as a single wide link, or
> multiple independent narrower links (e.g. x8 or x4+x4 mode on the Glymur
> PCIe3 PHY).
> 
> Earlier revisions tried to extend the existing single-instance
> phy-qcom-qmp-pcie.c driver to cover this hardware. That added a large
> amount of conditional, multi-PHY logic to a driver whose data model
> assumes one PHY per node.
> 
> [...]

Applied, thanks!

[1/5] arm64: dts: qcom: glymur: Add PCIe3 PHY and PCIe3a controller nodes
      commit: 7a147b572a22efb1404249f74d982ea386f59774
[2/5] arm64: dts: qcom: glymur-crd: Add PHY supplies for pcie3_phy
      commit: 5d9046549e433257f7fcc5d59a9a449c8c11dd84
[3/5] arm64: dts: qcom: mahua: Replace pcie3a/pcie3_phy with dedicated pcie3b_phy
      commit: f4526f9ee3146224d94907b38c712177d9c74df7
[4/5] arm64: dts: qcom: mahua-crd: Add PHY supplies for pcie3b_phy
      commit: fd452641dfebc13da4a44ef5a0417e4480b0e0a3

Best regards,
-- 
Bjorn Andersson <andersson@xxxxxxxxxx>