Re: [PATCH v1 1/4] dt-bindings: Add CIX Sky1 USB bindings

[Krzysztof Kozlowski]

On 31/08/2026 10:23, Hongliang Yang wrote:
> Add device tree bindings for CIX Sky1 USB3 PHY and Cadence USBSSP
> controller glue layer.
> 
> Signed-off-by: Hongliang Yang <hongliang.yang@xxxxxxxxxxx>
> ---
>  .../bindings/phy/cix,sky1-usb3-phy.yaml       | 109 +++++++++++++
>  .../bindings/usb/cix,sky1-usbssp.yaml         | 153 ++++++++++++++++++

Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters

A nit, subject: drop second/last, redundant "bindings". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst#L23

And do not combine USB patches with other subsystems.

>  MAINTAINERS                                   |   3 +
>  3 files changed, 265 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml
>  create mode 100644 Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml
> new file mode 100644
> index 000000000000..76d020df72dd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml
> @@ -0,0 +1,109 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/cix,sky1-usb3-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: CIX Sky1 USB3 PHY
> +
> +maintainers:
> +  - Hongliang Yang <hongliang.yang@xxxxxxxxxxx>
> +
> +description:
> +  The CIX Sky1 USB3 PHY is a multi-port SuperSpeedPlus PHY that
> +  supports up to two USB3 lanes. Each port is represented as a
> +  child node of the PHY controller.

Please read and follow DTS coding style.

> +
> +properties:
> +  compatible:
> +    const: cix,sky1-usb3-phy
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: APB register interface clock
> +      - description: PHY reference clock
> +
> +  clock-names:
> +    items:
> +      - const: apb_clk
> +      - const: ref_clk
> +
> +  resets:
> +    items:
> +      - description: PHY reset
> +      - description: PHY APB preset
> +
> +  reset-names:
> +    items:
> +      - const: reset
> +      - const: preset
> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 0
> +
> +patternProperties:
> +  "^usb-port@[0-9a-f]+$":
> +    type: object
> +    description:
> +      A single USB3 PHY port/lane.
> +
> +    properties:
> +      reg:
> +        maxItems: 1
> +
> +      "#phy-cells":
> +        const: 0
> +
> +    required:
> +      - reg
> +      - "#phy-cells"
> +
> +    additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - resets
> +  - reset-names
> +  - "#address-cells"
> +  - "#size-cells"
> +
> +unevaluatedProperties: false

Which other schema do you want to reference?

> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/cix,sky1.h>
> +    #include <dt-bindings/reset/cix,sky1-s5-system-control.h>
> +
> +    usb-phy@9210000 {
> +        compatible = "cix,sky1-usb3-phy";
> +        reg = <0x09210000 0x40000>;
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        resets = <&s5_syscon SKY1_USBPHY_SS_RST_N>,
> +                 <&s5_syscon SKY1_USBPHY_SS_PST_N>;
> +        reset-names = "reset", "preset";
> +
> +        clocks = <&scmi_clk CLK_TREE_USB3A_PHY3_GATE>,
> +                 <&scmi_clk CLK_TREE_USB3A_PHY_x2_REF>;
> +        clock-names = "apb_clk", "ref_clk";
> +
> +        usb-port@0 {
> +            reg = <0>;
> +            #phy-cells = <0>;
> +        };
> +
> +        usb-port@1 {
> +            reg = <1>;
> +            #phy-cells = <0>;
> +        };
> +    };
> diff --git a/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml b/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml
> new file mode 100644
> index 000000000000..47202ff5b9e5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml
> @@ -0,0 +1,153 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/cix,sky1-usbssp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: CIX Sky1 Cadence USBSSP Controller
> +
> +maintainers:
> +  - Hongliang Yang <hongliang.yang@xxxxxxxxxxx>
> +
> +description:
> +  The CIX Sky1 USBSSP controller is based on the Cadence USBSSP DRD
> +  controller. The integration adds glue registers and mode strap controls
> +  in the Sky1 S5 system controller. The CIX glue node wraps a Cadence
> +  USBSSP core as a child node.
> +
> +properties:
> +  compatible:
> +    const: cix,sky1-usbssp
> +
> +  reg:
> +    items:
> +      - description: AXI property configuration register
> +      - description: Controller status register

Registers are not address spaces. Devices do not have address spaces of
one register, so this is not a real device.


> +
> +  reg-names:
> +    items:
> +      - const: axi_property

axi

> +      - const: controller_status

controller



> +
> +  clocks:
> +    items:
> +      - description: Start-of-frame clock
> +      - description: AXI bus clock
> +      - description: Low-power mode clock
> +      - description: APB register interface clock
> +
> +  clock-names:
> +    items:
> +      - const: sof_clk
> +      - const: usb_aclk
> +      - const: lpm_clk
> +      - const: usb_pclk
> +
> +  resets:
> +    items:
> +      - description: APB register reset
> +      - description: Controller reset
> +
> +  reset-names:
> +    items:
> +      - const: usb_preset
> +      - const: usb_reset
> +
> +  cix,usb_syscon:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      Phandle to the Sky1 S5 system controller used to program USB mode
> +      strap controls.

So this is part of that device most likely.

> +
> +  axi_bmax_value:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 0x7
> +    description:
> +      AXI bus maximum burst length configuration value.
> +
> +  "#address-cells":
> +    const: 2
> +
> +  "#size-cells":
> +    const: 2
> +
> +  ranges: true
> +
> +patternProperties:
> +  "^usb-controller@[0-9a-f]+$":

Why using completely different names than entire Linux kernel?

> +    $ref: cdns,usb3.yaml#
> +    description:
> +      The Cadence USBSSP core controller node. See cdns,usb3.yaml
> +      for properties such as dr_mode, maximum-speed, phys, and interrupts.

Redundant description.

> +    unevaluatedProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - clocks
> +  - clock-names
> +  - resets
> +  - reset-names
> +  - cix,usb_syscon
> +  - "#address-cells"
> +  - "#size-cells"
> +  - ranges
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/cix,sky1.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/reset/cix,sky1-s5-system-control.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        usb@91c0300 {
> +            compatible = "cix,sky1-usbssp";
> +            #address-cells = <2>;
> +            #size-cells = <2>;
> +            ranges;
> +
> +            reg = <0x00 0x091c0314 0x00 0x4>,
> +                  <0x00 0x091c0400 0x00 0x4>;

Nope. You do not have a device with two registers.


Best regards,
Krzysztof