Re: [PATCH v8 04/12] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250

[Sreeshankar K]

On Tue, 1 Sept 2026 at 12:51, Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx> wrote:
>
> On 26-09-01 07:07:09, Sreeshankar K wrote:
> > Add support for the global clock controller found on SM7250
> > based devices.
> >
> > Signed-off-by: Sreeshankar K <sreeshankar0910@xxxxxxxxx>
> > ---
> >  drivers/clk/qcom/Kconfig      |    9 +
> >  drivers/clk/qcom/Makefile     |    1 +
> >  drivers/clk/qcom/gcc-sm7250.c | 2275 +++++++++++++++++++++++++++++++++
> >  3 files changed, 2285 insertions(+)
> >  create mode 100644 drivers/clk/qcom/gcc-sm7250.c
> >
>
> [...]
>
> > diff --git a/drivers/clk/qcom/gcc-sm7250.c b/drivers/clk/qcom/gcc-sm7250.c
> > new file mode 100644
> > index 000000000..0d548fe4a
> > --- /dev/null
> > +++ b/drivers/clk/qcom/gcc-sm7250.c
> > @@ -0,0 +1,2275 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
> > + * Copyright (c) 2026, Sreeshankar K <sreeshankar0910@xxxxxxxxx>
> > + */
>
> [...]
>
> > +
> > +static struct clk_alpha_pll gpll0 = {
> > +     .offset = 0x0,
> > +     .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
> > +     .clkr = {
> > +             .enable_reg = 0x52010,
> > +             .enable_mask = BIT(0),
> > +             .hw.init = &(struct clk_init_data){
>
> const
>
> I think I already mentioned this for v4.
>
> > +                     .name = "gpll0",
> > +                     .parent_data = &(const struct clk_parent_data){
> > +                             .index = DT_BI_TCXO,
> > +                     },
> > +                     .num_parents = 1,
> > +                     .ops = &clk_alpha_pll_fixed_lucid_ops,
> > +             },
> > +     },
> > +};
> > +
> > +static const struct clk_div_table post_div_table_gpll0_out_even[] = {
> > +     { 0x1, 2 },
> > +     { }
> > +};
> > +
> > +static struct clk_alpha_pll_postdiv gpll0_out_even = {
> > +     .offset = 0x0,
> > +     .post_div_shift = 8,
> > +     .post_div_table = post_div_table_gpll0_out_even,
> > +     .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
> > +     .width = 4,
> > +     .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
> > +     .clkr.hw.init = &(struct clk_init_data){
>
> Same here and everywhere else.
>
> > +             .name = "gpll0_out_even",
> > +             .parent_hws = (const struct clk_hw*[]){
> > +                     &gpll0.clkr.hw,
> > +             },
> > +             .num_parents = 1,
> > +             .ops = &clk_alpha_pll_postdiv_lucid_ops,
> > +     },
> > +};
>
> [...]

I apologize for my carelessness. I edited the source as per the
instruction and sent the patch in v6 patchset.
Link: https://lore.kernel.org/linux-arm-msm/20260824150156.1310-5-sreeshankar0910@xxxxxxxxx
I accidently applied the old patch from v5 patchset to v8 patchset. I
will send a completely fixed patchset as v9.

Regards,
Sreeshankar K