Re: [PATCH v5 02/16] media: ov8858: support 19.2 MHz clock and CHT gain setup

[Andy Shevchenko]

On Mon, Aug 31, 2026 at 08:00:47PM +0200, Maurizio Casciano wrote:
> The Yoga Book drives its OV8858 from a 19.2 MHz platform clock, while
> the existing mode tables program the sensor PLL for 24 MHz. Reusing
> those settings produces incorrect internal and CSI-2 clocks.
> 
> Accept both input rates and use the actual rate for the reset delay. For
> 19.2 MHz, apply the Cherry Trail MRD PLL and black-level settings after
> the generic mode table.
> 
> The 19.2 MHz platform uses the per-channel manual white-balance
> registers for digital gain. Program registers 0x5032, 0x5034 and 0x5036
> and expose their 1x-to-4x range, while retaining the existing
> long-exposure gain block for 24 MHz systems.
> 
> The manual white-balance register definitions and programming follow
> the GPL-2.0 Intel OV5670 driver, so retain its 2017 Intel copyright
> notice in this file. No proprietary source or tuning binary is included.
> 
> Tested on the Lenovo Yoga Book YB1-X91L OV8858 with full-range test bars
> and real 10-bit Bayer frames.

...

> -#define OV8858_LINK_FREQ		360000000U
> -#define OV8858_XVCLK_FREQ		24000000
> +#define OV8858_LINK_FREQ		(360 * HZ_PER_MHZ)
> +#define OV8858_XVCLK_FREQ		(24 * HZ_PER_MHZ)
> +#define OV8858_XVCLK_FREQ_19_2MHZ	(192 * HZ_PER_MHZ / 10)

No. I told you already few times this...

In the given context of the change I expect to see either all in plain numbers

#define OV8858_LINK_FREQ		360000000U
#define OV8858_XVCLK_FREQ_24MHz		24000000
#define OV8858_XVCLK_FREQ_19_2MHz	19200000

or only first one converted

#define OV8858_LINK_FREQ		(360 * HZ_PER_MHZ)
#define OV8858_XVCLK_FREQ_24MHz		24000000
#define OV8858_XVCLK_FREQ_19_2MHz	19200000

And better to name XVCLK definitions less ambiguous.

(Also read this https://gruhn.me/blog/2026-08-03/)

-- 
With Best Regards,
Andy Shevchenko