Re: [PATCH v5 00/20] iio: adc: Add AD7768/AD7768-4 ADC driver support
From: Jonathan Cameron
Date: Tue Sep 01 2026 - 12:57:28 EST
On Tue, 1 Sep 2026 01:32:45 -0700
Bartosz Golaszewski <brgl@xxxxxxxxxx> wrote:
> On Fri, 28 Aug 2026 17:30:23 +0200, Janani Sunil <janani.sunil@xxxxxxxxxx> said:
> > Add support for Analog Devices AD7768 and AD7768-4, 24-bit simultaneous
> > sampling Sigma-Delta ADCs with automatic power mode selection.
> >
> > Datasheet:
> > https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-ad7768-4.pdf
> >
> > **Device Overview:**
> > The AD7768 is an 8-channel, 24-bit simultaneous sampling ADC. The
> > AD7768-4 is a 4-channel variant. Both support configurable power modes,
> > programmable decimation filters, and a high-speed serial interface with
> > 1, 2, 4, or 8 data output lines. Per-channel offset, gain, and phase
> > calibration registers are available.
> >
> > **Features Implemented:**
> > - Support for AD7768 (8-channel) and AD7768-4 (4-channel) via device
> > match data.
> > - Automatic low-noise power mode selection (fast, median, low power)
> > with associated decimation rate and output data rate tables.
> > - Per-channel offset, gain, and conversion delay via IIO attributes.
> > - SPI communication with custom regmap bus for the device's protocol.
> > - IIO backend integration with adi-axi-adc for high-speed data capture.
> > - CRC data integrity verification over the serial interface.
> > - GPIO auxiliary driver to expose the 5 on-chip GPIO pins.
> > - VCM common-mode output exposed through the regulator framework, with
> > runtime PM management while the output is enabled.
> >
> > **Patch Summary:**
> > 1. Initialize the AXI ADC state mutex.
> > 2. Add the AD7768 and AD7768-4 devicetree binding.
> > 3. Add the IIO backend CRC operation.
> > 4. Implement CRC control in the AXI ADC backend.
> > 5. Add core AD7768 and AD7768-4 capture support.
> > 6. Validate the master clock rate.
> > 7. Add the power-mode configuration helper.
> > 8. Derive output data rates and the data-clock divider.
> > 9. Configure enabled channels across two sampling profiles.
> > 10. Expose per-channel sampling-frequency controls.
> > 11. Expose per-channel filter controls.
> > 12. Wait for active digital filters to settle.
> > 13. Add per-channel offset and gain calibration controls.
> > 14. Add per-channel conversion delay.
> > 15. Expose the VCM output through the regulator framework.
> > 16. Register the GPIO auxiliary device from the parent driver.
> > 17. Use regmap_test_bits() for single-bit gpio-regmap reads.
> > 18. Add optional runtime PM support to gpio-regmap.
> > 19. Add the AD7768 GPIO auxiliary driver.
> > 20. Add driver documentation.
>
> What is the merge strategy here between iio and GPIO trees? Can patches
> 17-18 go through an immutable branch in the GPIO tree that would be merged
> into the iio tree?
I don't think there is any coupling between those and the rest of the
series. Janani can you confirm if these two patches can go via GPIO
whilst the rest go via IIO (without the GPIO patches)?
Obviously the GPIO driver won't ever bind to anything until the two come
together but build tests etc should be fine.
Jonathan
>
> Bart